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5
LPDDR4_VDDQ
C192
C193
C194
C195
C196
C197
C198
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
16V
16V
D
C162
C163
C164
C165
C166
C167
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
16V
LPDDR4_VDD2
C206
C207
C208
C209
C210
C211
C171
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
16V
16V
C174
C175
C156
C157
C158
C160
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
16V
C
VCCIO3
U3D
R18
VCCIO3
PB110A/VREF3_1/ADC_CP10
U18
VCCIO3
V16
VCCIO3
PB112A/PCLKT3_0/ADC_CP4
PB112B/PCLKC3_0/ADC_CN4
C58
C59
C60
PB118A/PCLKT3_1/COMP2IP
0.1uF
0.1uF
0.1uF
PB118B/PCLKC3_1/COMP2IN
B
VCCIO3
C61
10uF
PB148A/PCLKT3_2/COMP3IP
PB148B/PCLKC3_2/COMP3IN
A
PB154A/PCLKT3_3/ADC_CP15
PB154B/PCLKC3_3/ADC_CN15
PB156A/LRC_GPLL0T_IN
PB156B/LRC_GPLL0C_IN/VREF3_2
LFMXO5-100-BBG400
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02058-1.0
4
+1.8V
C199
C159
MPZ1005S121CT000
0.1uF
0.1uF
16V
16V
FB16
LPDDR4_VDD1
C190
22uF
C168
C169
C170
C200
C201
C202
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
+1.1V
16V
16V
16V
16V
16V
16V
MPZ1005S121CT000
FB17
C186
22uF
C203
C204
C205
C172
C173
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
MPZ1005S121CT000
FB18
C188
C161
C176
C177
22uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
Fly by topology for CA/CK/CKE/CS
LPDDR4_CK_T
R252
LPDDR4_DQ21
W16
Reserve termination under Channel A
LPDDR4_DQ16
Y16
PB110B/ADC_CN10
LPDDR4_DQ17
Y17
R259
49.9E
LPDDR4_DMI2
W17
DNI
LPDDR4_DQS2_T
Y19
R258
49.9E
PB114A/COMP1IP
LPDDR4_DQS2_C
Y18
DNI
PB114B/COMP1IN
LPDDR4_DQ20
V17
R257
49.9E
PB116A/ADC_CP8
LPDDR4_DQ22
U17
DNI
PB116B/ADC_CN8
LPDDR4_DQ18
T17
R256
49.9E
LPDDR4_DQ19
R17
DNI
LPDDR4_DQ23
T16
R255
49.9E
PB120A/ADC_CP13
LPDDR4_ODT_A
R16
DNI
PB120B/ADC_CN13
LPDDR4_ODT_B
W15
R254
49.9E
PB122A
LPDDR4_DQ13
W14
DNI
PB122B
LPDDR4_DQ14
V15
R253
49.9E
PB124A
LPDDR4_DQ12
V14
DNI
PB124B
LPDDR4_DQS1_T
Y15
PB126A
LPDDR4_DQS1_C
Y14
PB126B
LPDDR4_DMI1
U15
PB128A
LPDDR4_DQ15
U14
PB128B
LPDDR4_DQ11
T15
PB130A
LPDDR4_DQ9
T14
PB130B
LPDDR4_DQ10
LVSTLD_100MHzp
R14
R195
PB132A
LPDDR4_DQ8
R15
DNI
PB132B
LPDDR4_RESET_N
N16
PB134A
LPDDR4_DQ4
P16
PB134B
LPDDR4_DQ6
+3.3V
M17
PB136A
LPDDR4_DQ7
M16
MPZ1005S121CT000
PB136B
LPDDR4_DQS0_T
P19
PB138A
LPDDR4_DQS0_C
P20
PB138B
LPDDR4_DQ3
P17
FB11
PB140A
LPDDR4_DQ2
P18
PB140B
LPDDR4_DMI0
N17
R52
PB142A
LPDDR4_DQ0
N18
PB142B
LPDDR4_DQ1
N20
PB144A
LPDDR4_DQ5
N19
PB144B
LPDDR4_CS0
W18
10K
PB146A/ADC_CP14
LPDDR4_CA1
V18
PB146B/ADC_CN14
LPDDR4_CK_T
R19
LPDDR4_CK_C
R20
LPDDR4_CA4
V20
PB150A/ADC_CP11
LPDDR4_CKE0
W20
PB150B/ADC_CN11
LPDDR4_CA2
T19
PB152A/ADC_CP12
LPDDR4_CA5
T20
LPDDR4_CA3
PB152B/ADC_CN12
V19
LPDDR4_CA0
W19
LVSTLD_100MHzp
U19
LVSTLD_100MHzn
U20
4
Figure A. 6. LPDDR4 (BANK3)
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
U9A
LPDDR4_VDD1
LPDDR4_DQ0
B2
LPDDR4_DQ1
DQ0_A
VDDQ
C2
DQ1_A
VDDQ
LPDDR4_DQ2
E2
DQ2_A
VDDQ
LPDDR4_DQ3
F2
DQ3_A
VDDQ
LPDDR4_DQ4
C191
C306
C307
F4
LPDDR4_DQ5
DQ4_A
VDDQ
E4
DQ5_A
VDDQ
LPDDR4_DQ6
1uF
22uF
1uF
C4
DQ6_A
VDDQ
LPDDR4_DQ7
50V
50V
B4
DQ7_A
VDDQ
LPDDR4_DMI0
C3
LPDDR4_DQS0_T
DMI0_A
VDDQ
D3
DQS0_T_A
VDDQ
LPDDR4_DQS0_C
E3
DQS0_C_A
LPDDR4_VDDQ
LPDDR4_DQ8
B11
LPDDR4_DQ9
DQ8_A
C11
DQ9_A
LPDDR4_DQ10
E11
DQ10_A
LPDDR4_DQ11
C187
C308
C309
F11
DQ11_A
LPDDR4_DQ12
F9
DQ12_A
LPDDR4_DQ13
1uF
22uF
1uF
E9
DQ13_A
LPDDR4_DQ14
50V
50V
C9
DQ14_A
LPDDR4_DQ15
B9
DQ15_A
LPDDR4_DMI1
C10
DMI1_A
LPDDR4_VDD2
LPDDR4_DQS1_T
D10
DQS1_T_A
LPDDR4_DQS1_C
E10
DQS1_C_A
LPDDR4_CA0
H2
CA0_A
LPDDR4_CA1
C189
C310
C311
J2
CA1_A
LPDDR4_CA2
H9
CA2_A
LPDDR4_CA3
H10
1uF
22uF
1uF
LPDDR4_CA4
CA3_A
H11
50V
50V
CA4_A
LPDDR4_CA5
J11
CA5_A
LPDDR4_CK_T
J8
CK_T_A
LPDDR4_CK_C
J9
CK_C_A
LPDDR4_CKE0
J4
CKE0_A
LPDDR4_CK_C
LPDDR4_CS0
150
H4
CS0_A
LPDDR4_ODT_A
G2
ODT_CA_A
Need enable ODT in the Channel A
A1
DNU_A1
LPDDR4_CS0
A11
DNU_A11
A12
DNU_A12
LPDDR4_CA0
A2
DNU_A2
B1
LPDDR4_CA1
DNU_B1
B12
DNU_B12
LPDDR4_CA2
A8
LPDDR4_VDDQ
LPDDR4_CA3
NC_A8
G11
NC_G11
H3
NC_H3
LPDDR4_CA4
J5
NC_J5
K5
R138
LPDDR4_CA5
NC_K5
K8
NC_K8
240E
ZQ0
A5
ZQ0
LVSTLD_100MHzn
100
lpddr4-fbga200-x32
Close to U3
LPDDR4 x16
C302
C303
100nF
10nF
16V
50V
X8
1
EN
HCSL_100MHzp
4
R241
0
Q
HCSL_100MHzn
2
5
R242
0
NC
Q_N
LVSTLD_100MHzp
HCSL_100MHzp
100MHz
C28
10nF
50V
LVSTLD_100MHzn
HCSL_100MHzn
C87
10nF
50V
3
MachXO5T-NX-Development Board
Evaluation Board User Guide
2
1
U9B
LPDDR4_VDDQ
LPDDR4_DQ16
AA2
DQ0_B
VDDQ
LPDDR4_DQ17
B3
Y2
LPDDR4_DQ18
DQ1_B
VDDQ
B5
V2
DQ2_B
VDDQ
LPDDR4_DQ19
B8
U2
DQ3_B
VDDQ
LPDDR4_DQ20
B10
U4
DQ4_B
VDDQ
LPDDR4_DQ21
D1
V4
LPDDR4_DQ22
DQ5_B
VDDQ
D5
Y4
DQ6_B
VDDQ
LPDDR4_DQ23
D8
AA4
DQ7_B
VDDQ
LPDDR4_DMI2
D12
Y3
DMI0_B
VDDQ
LPDDR4_DQS2_T
F3
W3
LPDDR4_DQS2_C
DQS0_T_B
VDDQ
LPDDR4_VDD1
F10
V3
DQS0_C_B
VDD1
F1
AA11
VDD1
DQ8_B
VDD1
F12
Y11
VDD1
DQ9_B
VDD1
G4
V11
VDD1
DQ10_B
VDD1
LPDDR4_VDD2
G9
U11
VDD1
DQ11_B
U9
DQ12_B
VDD2
A4
V9
VDD2
DQ13_B
VDD2
A9
Y9
VDD2
DQ14_B
VDD2
F5
AA9
VDD2
DQ15_B
VDD2
F8
Y10
VDD2
DMI1_B
VDD2
H1
W10
VDD2
DQS1_T_B
VDD2
H5
V10
VDD2
DQS1_C_B
VDD2
H8
VDD2
VDD2
LPDDR4_CA0
H12
R2
VDD2
CA0_B
VDD2
LPDDR4_CA1
K1
P2
VDD2
CA1_B
VDD2
LPDDR4_CA2
K3
R9
VDD2
CA2_B
VDD2
LPDDR4_CA3
K10
R10
VDD2
CA3_B
VDD2
LPDDR4_CA4
K12
R11
VDD2
LPDDR4_CA5
CA4_B
P11
CA5_B
VSS
LPDDR4_CK_T
A3
P8
VSS
CK_T_B
VSS
LPDDR4_CK_C
A10
P9
VSS
CK_C_B
VSS
LPDDR4_CKE0
C1
P4
VSS
CKE0_B
VSS
LPDDR4_CS0
C5
R4
VSS
CS0_B
VSS
LPDDR4_ODT_B
C8
T2
VSS
ODT_CA_B
VSS
C12
VSS
VSS
D2
VSS
VSS
D4
VSS
VSS
D9
AA1
VSS
DNU_AA1
VSS
D11
AA12
VSS
DNU_AA12
VSS
E1
AB1
VSS
DNU_AB1
VSS
E12
AB2
VSS
DNU_AB2
VSS
E5
AB11
VSS
DNU_AB11
VSS
E8
AB12
VSS
DNU_AB12
VSS
G1
VSS
VSS
G10
N5
VSS
NC_N5
VSS
G12
N8
VSS
NC_N8
VSS
G3
P5
VSS
NC_P5
VSS
G5
R3
VSS
NC_R3
VSS
G8
VSS
VSS
J1
VSS
VSS
J3
VSS
VSS
J10
VSS
VSS
J12
VSS
VSS
K2
VSS
VSS
K4
VSS
VSS
K9
VSS
VSS
LPDDR4_RESET_N
K11
T11
VSS
RESET_N
VSS
VSS
R139
10K
lpddr4-fbga200-x32
Defualt populate x16 bits LPDDR4
Reserve Future Usage with x24 bits options
DO NOT USE Channel B now
R238
R239
49.9E
49.9E
L L L a a a t t t t t t i i i c c c e e e S S S e e e m m m i i i c c c o o o n n n d d d u u u c c c t t t o o o r r r A A A p p p p p p l l l i i i c c c a a a t t t i i i o o o n n n s s s
E E E m m m a a a i i i l l l : : : t t t e e e c c c h h h s s s u u u p p p p p p o o o r r r t t t @ @ @ L L L a a a t t t t t t i i i c c c e e e s s s e e e m m m i i i . . . c c c o o o m m m
P P P h h h o o o n n n e e e ( ( ( 5 5 5 0 0 0 3 3 3 ) ) ) 2 2 2 6 6 6 8 8 8 - - - 8 8 8 0 0 0 0 0 0 1 1 1 - - - o o o r r r - - - ( ( ( 8 8 8 0 0 0 0 0 0 ) ) ) L L L A A A T T T T T T I I I C C C E E E
T T T i i i t t t l l l e e e
L L L P P P D D D D D D R R R 4 4 4 ( ( ( B B B A A A N N N K K K 3 3 3 ) ) )
S S S i i i z z z e e e
P P P r r r o o o j j j e e e c c c t t t
B B B
M M M a a a c c c h h h X X X O O O 5 5 5 - - - N N N X X X 1 1 1 0 0 0 0 0 0 K K K D D D e e e v v v e e e l l l o o o p p p m m m e e e n n n t t t B B B o o o a a a r r r d d d
D D D a a a t t t e e e : : :
F F F r r r i i i d d d a a a y y y , , , F F F e e e b b b r r r u u u a a a r r r y y y 1 1 1 7 7 7 , , , 2 2 2 0 0 0 2 2 2 3 3 3
2
1
LPDDR4_VDDQ
U3
U10
W1
W5
W8
W12
AA3
AA5
D
AA8
AA10
LPDDR4_VDD1
T4
T9
U1
LPDDR4_VDD2
U12
N1
N3
N10
N12
R1
R12
R5
R8
U5
U8
AB4
AB9
N2
N4
N9
C
N11
P1
P3
P10
P12
T1
T3
T5
T8
T10
T12
V1
V5
V8
V12
W2
W4
W9
W11
Y1
Y5
Y8
Y12
AB3
B
AB5
AB8
AB10
A
1 1 1 . . . 0 0 0
S S S c c c h h h e e e m m m a a a t t t i i i c c c R R R e e e v v v
B B B o o o a a a r r r d d d R R R e e e v v v
A A A
S S S h h h e e e e e e t t t
6 6 6
o o o f f f
1 1 1 1 1 1
49
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