J1 Male Header; Table 9.1. J1 Male Header Connections For Use With Machxo3-9400 Or Ecp5 Versa Develpment Board - Lattice Semiconductor ASC Bridge Board User Manual

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9. J1 Male Header

The J1 male header provides power pins and additional I/Os from either the MachXO3-9400 Development Board or the
ECP5 Versa Development Board's expansion connector which are not connected to the ASC Breakout Board
connectors.

Table 9.1. J1 Male Header Connections for use with MachXO3-9400 or ECP5 Versa Develpment Board

J1 Pin
Silkscreen
Number
Name
1
+3.3 V
2
+2.5 V
3
N.C.
4
EXPCON_OSC
5
EXPCON_CLKIN
6
EXPCON_CLKOUT
7
HPE_RESOUT#
8
EXPCON_IO0
9
EXPCON_IO2
10
EXPCON_IO14
11
EXPCON_IO17
12
CARDSEL#
13
GND
14
GND
15
GND
16
GND
17
GND
18
GND
19
GND
20
GND
21
GND
22
GND
23
GND
24
GND
Notes:
When using the MachXO3-9400 Development Board the J1 pin 4 signal EXPCON_OSC comes from either the on-board oscillator
Y2 or from an off-board source using J10.
When using the ECP5 Versa Development Board the J1 pin 4 signal EXPCON_OSC comes from the on-board Lattice
ispClock5406D device.
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02025-2.0
MachXO3-9400
Ball
Port
––
––
––
1
(Note)
A10
PT23B
A21
PT44A
G9
PT21D
F8
PT11C
F9
PT21C
C6
PT14C
D8
PT15B
C13
PT29C
––
––
––
––
––
––
––
––
––
––
––
––
Evaluation Board User Guide
ECP5-45
Ball
Port
––
––
––
2
(Note)
A10
PT36A
E11
PT42B
A8
PT18B
A12
PT49A
B13
PT51A
A9
PT33A
B15
PT69A
A7
PT18A
––
––
––
––
––
––
––
––
––
––
––
––
ASC Bridge Board
FPGA Board
Signal Name
––
––
––
EXPCON_OSC
EXPCON_CLKIN
EXPCON_CLKOUT
HPE_RESOUT#
EXPCON_IO0
EXPCON_IO2
EXPCON_IO12
EXPCON_IO16
CARDSEL#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
11

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