Appendix A. Machxo5T-Nx Development Board Schematics; Figure A. 1. Title Page - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

MachXO5T-NX-Development Board
Evaluation Board User Guide

Appendix A. MachXO5T-NX Development Board Schematics

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MachXO5-NX 100K Development Board
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01 - Title Page
02 - Block Diagram and Power Tree
C
03 - USB to Hard JTAG I/F
04 - USB to Soft JTAG I/F (BANK0)
05 - PMOD0/Versa connector (BANK1/2)
06 - LPDDR4 (BANK3)
B
07 - PCIE&FPC Headers (BANK4)
08 - GBE and RJ45 (BANK5)
09 - Multiple Headers (BANK6/7)
10 - POWER RAILS
A
11 - POWER REGULATORS
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Rev - A
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Figure A. 1. Title Page

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FPGA-EB-02058-1.0