Pcie Gold Finger; Figure 7.1. Top Side Of Pcie Edge Connector; Table 7.1. Gold Finger Pin Connections - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

7. PCIe Gold Finger

MachXO5T-NX Development Board supports ×1 PCIe Gen2, as shown in
Table 7.1.

Table 7.1. Gold Finger Pin Connections

CN1 Pin Number
A1
A2,A3,B1,B2,B3
A4,A12,A15,A18,B4,B7,B13,B16,B18
A9,A10,B8
A11
A13
A14
A16
A17
B14
B15
B17
—
—
Note:
1. Need add JP10 to bridge with FPGA control I/O.
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FPGA-EB-02058-1.0

Figure 7.1. Top Side of PCIe Edge Connector

Net Name
PRSNT1n
12_IN_PCIE
GND
PCIE_3V3
PCIE_PERSTn
PCIE_CLKP
PCIE_CLKN
x1_PERp0
x1_PERn0
x1_PETp0
x1_PETn0
PRSNT2n
R0_ext
RET0_ref
MachXO5T-NX-Development Board
Evaluation Board User Guide
Figure 7.1. The signal connections are listed in
LFMXO5-100T Ball Location
—
—
—
—
1
K6
C7
B7
A5
A6
A2
A3
—
C4
B4
21