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MachXO5T-NX-Development Board
Evaluation Board User Guide
Appendix D. MachXO5T-NX Development Board Errata
As shown in
Appendix A. MachXO5T-NX Development Board
•
Page3 of the Schematics, USB to Hard JTAG I/F
Pin 1 of J1 and Pin 15 of U14 are connected with VCCIO2. It is recommended to connect them with VCCIO1 to
ensure JTAG pins pull up to VCCIO1.
•
Page 7 of the Schematics, PCIE&FPC Headers (BANK4)
PCIE_CLKp and PCIE_CLKn assignments are mismatched with the U3 ball locations. It is recommended to swap
them with the correct assignment. PCIE_CLKp should be connected to B7 of U3. PCIE_CLKn should be connected to
C7 of U3.
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68
Schematics:
FPGA-EB-02058-1.0
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