Jtag Download Interface; Figure 3.3. Level Shift For Jtag Download Interface; Figure 3.4. Jtag Test Header - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

MachXO5T-NX-Development Board
Evaluation Board User Guide

3.1. JTAG Download Interface

A level shifter SN74AVC4T774 U14 from TI is inserted between Config FTDI Port A and LFMXO5-100T JTAG port to make
sure the FTDI fixed I/O voltage can adapt with flexible voltage selection of bank 2 of the FPGA, as shown in Figure 3.3.
An eight-pin header J1 (Figure 3.4) allowing you to probe the JTAG signals to access LFMXO5-100T JTAG port from the
external JTAG host, such as external Lattice HW-USBN-2B Programming Cable (available separately), or to access SSPI
port from the external SPI host. In those cases, jumper JP1 must be added to pull OEN high and ensure U14 to output
tri-state mode so as to avoid multi-drivers on those shared signals. The JTAG connections between J1 and
LFMXO5-100T are listed in Table 3.1.

Figure 3.3. Level Shift for JTAG Download Interface

Figure 3.4. JTAG Test Header

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