User I C Interface; Adc And Potentiometer; Table 12.11. J16 Header Pin Connections; Table 12.12. I C Connections - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

MachXO5T-NX-Development Board
Evaluation Board User Guide

Table 12.11. J16 Header Pin Connections

J16 Pin Number Net Name
1 PMOD1_1
2 PMOD1_2
3 PMOD1_3
4 PMOD1_4
5
6 VCCIO7
2
12.7. User I C Interface
This board provides more options for user I
headers. They are solid connected for target applications, but those connections to bridge SCL0/SDA0 are not
populated in default. User need to customize interconnection for I
2
want to use an Ardvark I C host to access ARDUINO board, you can use internal fabric logic of LFMXO5-100T to bridge
AK_SCL/AK_SDA with AR_SCL/AR_SDA, or add bridge resistors according to
SCL0/SDA0 for bridge interconnections on board without involvement of FPGA. You also need to setup the design with
tri-state mode for output high with pull up resistors. If there is no pull up setup on the counterpart boards or internal
GPIOs of FPGA, you can add JP12 and JP13 to leverage FTDI's I2C pull up R33 and R34 for SCL0/SDA0. Note that the
multi-drives should be disabled for FTDI_SCL/FTDI_SDA in this case. You can add JP9 to disable FTDI output and force
FPGA output High-Z from ball location A19/A18.
By adding JP12 and JP13, you can also access FPGA I
through SCL0/SDA0, which provides the flexibility to update the bitstream from an extension board in some
applications.
2
Table 12.12. I C Connections
Extend header
Versa Header
(J9)
Aardvark Header
(J7)
Arduino Header
(J2)
Raspberry Pi Header (J6)
Raspberry Pi Header (J6)

12.8. ADC and Potentiometer

There are two dedicate ADC input pairs for LFMXO5-100T. This board provides multiple application options. For default population,
one pair of ADC0 is used to measure the core VCC voltage drop through a 10 mΩ resistor R112. Therefore, the core VCC current is
calculable, as shown in Figure 12.1. Positive input of another pair ADC1 is connected to a 10 kΩ Trimmer Potentiometers (POT1)
which provides voltage variation from 0 V to selectable VCCIO4, as shown in
through 1 kΩ resistor.
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
LFMXO5-100T Ball
Location
J4
J1
H1
H3
GND —
—
2
C access from different LFMXO5-100T Wide Range I/O to multiple onboard
2
C configure interface from those extension boards with I
LFMXO5-100T Ball
LFMXO5-100T Bank
Location for JTAG
1
6
6
7
7
J16 Pin Number Net Name
7 PMOD1_5
8 PMOD1_6
9 PMOD1_7
10 PMOD1_8
11 GND
12 VCCIO7
2
C applications across the board. For example, if you
Table 12.12 to connect all of them to
Net Name
B20 EXPCON_IO13
G16 EXPCON_IO15
M7 AK_SCL
M9 AK_SDA
N5 AR_SCL
N6 AR_SDA
E1 RASP_ID_SC
D1 RASP_ID_SD
F6 RASP_IO03
E8 RASP_IO02
Figure 12.2. The negative input of ADC1 is grounded
LFMXO5-100T Ball
Location
J5
J3
J2
H2
—
—
2
C host
Bridge Resistor to
SCL0/SDA0
R35 (DNI)
R37 (DNI)
R60 (DNI)
R59 (DNI)
R45 (DNI)
R44 (DNI)
R85 (DNI)
R87 (DNI)
R96 (DNI)
R84 (DNI)
FPGA-EB-02058-1.0