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MachXO5T-NX-Development Board
Evaluation Board User Guide
5
J17
1
1
3
D
C143
C144
2
100nF
D17
PJ-051A
V12P10
12_IN_PCIE
+5.0V
U12
8
VIN
C105
C106
C113
R104
1
EN
4.7k
100nF
5
GND
3
VREG
C
C117
4
SS
1uF
C119
3.3nF
3.3V
+5.0V
U8
3
2
IN
OUT
4
TAB
C88
GND
1
NCV1117ST33T3G
B
2.5V
+5.0V
U13
3
2
IN
OUT
4
TAB
C104
GND
1
NCV1117ST25T3G
A
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
54
4
VBUS_5V
+12 V
+12V
PS_5V
SW6
1.5 A
1
U10
2
2
3
1
2
FUSE
C145
100nF
D16
V12P10
BD9D321EFJ
+1.0V
7
BOOT
C141
1.5uH SPM6530T-1R5M-HZ
6
100nF
SW
L9
2
C115
R102
C109
C110
FB
7.5k
0.1nF
22uF
22uF
R103
22k
Vout=0.76*(R102+R103)/R103
+3.3 V
1 A
+3.3V
R136
0
L4
3.3V_OUT
2
1
600ohm 500mA
C89
C90
22uF
100nF
+2.5 V
1 A
+2.5V
R98
0
L5
2.5V_OUT
2
1
600ohm 500mA
C91
C92
22uF
100nF
4
Figure A. 11. Power Regulators
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
+12V
+5.0V
U11
8
C107
C108
C114
R101
1
4.7k
100nF
5
3
R135
1K
C118
4
1uF
D18
C120
Blue
3.3nF
+1.0 V
3 A
+2.5V
R105 4.7k
C155
C103
100nF
10uF
RP115H181D/SOT89-5
+2.5V
R106 4.7k
C96
C97
100nF
10uF
RP111H121D-T1-FE/SOT89-5
1.1V
+1.1 v
500 mA
+2.5V
U17
4
5
Vdd
Vout
R145 4.7k
3
1
R54
0
CE
Vfb
C102
RP111H111D/SOT89-5
R53
23.7K-DNI
3
2
BD9D321EFJ
PS_5V
7
VIN
BOOT
C142
3.3uH SPM6530T-3R3M
EN
6
100nF
SW
L10
GND
2
C116
R99
C111
C112
VREG
FB
124k
0.1nF
22uF
22uF
SS
R100
22k
Vout=0.76*(R99+R100)/R100
1.8V
+1.8 V
1 A
+1.8V
U15
4
5
Vdd
Vout
3
1
R109
0
CE
Vfb
C152
C153
C154
R107
2.2uF
100nF
10uF
23.7K-DNI
1.2V
+1.2 V
+1.2V
500mA
U16
4
5
Vdd
Vout
3
1
R110
0
CE
Vfb
C93
C94
C95
R108
2.2uF
100nF
10uF
23.7K-DNI
+1.1V
C121
10uF
10V
L L L a a a t t t t t t i i i c c c e e e S S S e e e m m m i i i c c c o o o n n n d d d u u u c c c t t t o o o r r r A A A p p p p p p l l l i i i c c c a a a t t t i i i o o o n n n s s s
E E E m m m a a a i i i l l l : : : t t t e e e c c c h h h s s s u u u p p p p p p o o o r r r t t t @ @ @ L L L a a a t t t t t t i i i c c c e e e s s s e e e m m m i i i . . . c c c o o o m m m
P P P h h h o o o n n n e e e ( ( ( 5 5 5 0 0 0 3 3 3 ) ) ) 2 2 2 6 6 6 8 8 8 - - - 8 8 8 0 0 0 0 0 0 1 1 1 - - - o o o r r r - - - ( ( ( 8 8 8 0 0 0 0 0 0 ) ) ) L L L A A A T T T T T T I I I C C C E E E
T T T i i i t t t l l l e e e
P P P O O O W W W E E E R R R R R R E E E G G G U U U L L L A A A T T T O O O R R R S S S
S S S i i i z z z e e e
P P P r r r o o o j j j e e e c c c t t t
B B B
M M M a a a c c c h h h X X X O O O 5 5 5 - - - N N N X X X 1 1 1 0 0 0 0 0 0 K K K D D D e e e v v v e e e l l l o o o p p p m m m e e e n n n t t t B B B o o o a a a r r r d d d
D D D a a a t t t e e e : : :
F F F r r r i i i d d d a a a y y y , , , F F F e e e b b b r r r u u u a a a r r r y y y 1 1 1 7 7 7 , , , 2 2 2 0 0 0 2 2 2 3 3 3
2
1
+5.0 V
3 A
D
C
B
A
1 1 1 . . . 0 0 0
S S S c c c h h h e e e m m m a a a t t t i i i c c c R R R e e e v v v
B B B o o o a a a r r r d d d R R R e e e v v v
A A A
S S S h h h e e e e e e t t t
1 1 1 1 1 1
o o o f f f
1 1 1 1 1 1
1
FPGA-EB-02058-1.0
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