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MachXO5T-NX-Development Board
Evaluation Board User Guide
9. LPDDR4 Memory Controller Interface
Table 9.1
lists all LPDDR4 memory controller Interface signals. The LFMXO5-100T device Memory Controller is used to
interface with the onboard 16-bit parallel data and 8 Gb capacity LPDDR4 memory device (Micron MT53E512M16D1),
which is supported with 512 Meg ×16 configurations. This board is designed to use on-die termination in default and
reserved on-board termination options.
Table 9.1. LPDDR4 Memory Controller Interconnections
LPDDR4 Net Name (U9)
DQ0_A
DQ1_A
DQ2_A
DQ3_A
DQ4_A
DQ5_A
DQ6_A
DQ7_A
DMI0_A
DQS0_T_A
DQS0_C_A
DQ8_A
DQ9_A
DQ10_A
DQ11_A
DQ12_A
DQ13_A
DQ14_A
DQ15_A
DMI1_A
DQS1_T_A
DQS1_C_A
CA0_A
CA1_A
CA2_A
CA3_A
CA4_A
CA5_A
CK_T_A
CK_C_A
CKE0_A
CS0_A
ODT_CA_A
RESET_N
Note:
ZQ0 is pull up VDDQ through a 240 resistor.
1.
Caution:
The MachXO5T-NX Development Board is designed to support ×16 bits with default population but
reserved to support x24 bits configuration if change to x32 LPDDR4 device.
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
ZQ0
1
LFMXO5-100T Ball Location
N18
N20
P18
P17
P16
N19
M17
M16
N17
P19
P20
R15
T14
R14
T15
V14
W14
V15
U14
U15
Y15
Y14
W19
V18
T19
V19
V20
T20
R19
R20
W20
W18
R16
N16
—
FPGA-EB-02058-1.0
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