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MachXO5T-NX-Development Board
Evaluation Board User Guide
5
VCCPLLSD
VCCAUXSDQ
C20
C21
C22
C23
47uF
0.47uF
47uF
0.47uF
VCCAUXSDQ
10V
10V
RET0_ref
R0_ext
VCCSD
R127
976R-0402SMT
0.1%
D
VCCSDCK
VCCPLLSD
VCCAUXSDQ
C24
C25
C26
C27
47uF
0.47uF
47uF
0.47uF
10V
10V
RET3_ref
R3_ext
VCCSDCK
R128
1.15K-0402SMT
0.1%
VCCSD
VCCSD
C37
10uF
C52
C53
C54
10uF
0.1uF
0.1uF
EXT1_CLKp
C
EXT0_CLKp
VCCIO4
U3E
U11
VCCIO4
PB50A/VREF4_1
T8
VCCIO4
V8
VCCIO4
PB52A/PCLKT4_0
PB52B/PCLKC4_0
C82
C83
C84
0.1uF
0.1uF
0.1uF
PB58A/PCLKT4_1
PB58B/PCLKC4_1
B
VCCIO4
C80
10uF
PB98A/ADC_CP5
PB98B/ADC_CN5
PB100A/PCLKT4_2/ADC_CP7
PB100B/PCLKC4_2/ADC_CN7
PB102A/ADC_CP6
A
PB102B/ADC_CN6
PB104A/ADC_CP9
PB104B/ADC_CN9
PB106A/PCLKT4_3
PB106B/PCLKC4_3
PB108A
PB108B/VREF4_2
LFMXO5-100-BBG400
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50
4
SD0 are 85-ohm differential pair.
SD3 are 100-ohm differential pair.
VCCPLLSD
U3J
R0_ext
B1
C4
VCCPLLSD0
SD0_REXT
x1_PETp0
C9
A2
VCCPLLSD3
SD0_RXDP
x1_PETn0
D7
A3
VCCAUXSDQ0
SD0_RXDN
RET0_ref
C5
B4
VCCSD0
SD0_REFRET
C8
A5
C47
220NF-0402SMT
VCCSD3
SD0_TXDP
C6
A6
C48
220NF-0402SMT
VCCSDCK
SD0_TXDN
R3_ext
C10
SD3_REXT
SD3_RXp
A8
SD3_RXDP
SD3_RXn
A9
SD3_RXDN
RET3_ref
B10
SD3_REFRET
A11
C312 220NF-0402SMT
SD3_TXDP
A12
C313 220NF-0402SMT
SD3_TXDN
VCCSDCK
EXT0_CLKp
C11
SD_EXT0_REFCLKP
EXT0_CLKn
C12
SD_EXT0_REFCLKN
EXT1_CLKp
B13
SD_EXT1_REFCLKP
EXT1_CLKn
C38
C13
SD_EXT1_REFCLKN
PCIE_CLKp
C7
SDQ0_REFCLKN
PCIE_CLKn
0.1uF
B7
SDQ0_REFCLKP
LFMXO5-100-BBG400
EXT1_CLKn
R246
100
SW2
[9] SW2
DNI
EXT0_CLKn
R251
100
DNI
TP3
Close to U3
SLVS_DP9
U7
SLVS_DN9
V7
PB50B
SLVS_DP10
T7
SLVS_DN10
R7
SLVS_DP8
SLVS_TP1
Y6
PB54A
[8] SLVS_TP1
SLVS_DN8
Y7
PB54B
SLVS_DP20
SLVS_DP26
N7
PB56A
[8] SLVS_DP26
SLVS_DN20
SLVS_DN26
N8
PB56B
[8] SLVS_DN26
SLVS_DP18
W7
SLVS_DN18
SLVS_DP27
W8
[8] SLVS_DP27
SLVS_DP11
SLVS_DN27
R8
PB60A
[8] SLVS_DN27
SLVS_DN11
P8
PB60B
SLVS_DP19
SLVS_DP0
N9
PB62A
SLVS_DN19
SLVS_DN0
P9
PB62B
SLVS_DP17
R9
PB64A
SLVS_DN17
SLVS_DP1
T9
PB64B
SLVS_DP7
SLVS_DN1
Y8
PB66A
SLVS_DN7
Y9
PB66B
SLVS_DP16
SLVS_DP2
U9
PB80A
SLVS_DN16
SLVS_DN2
V9
PB80B
SLVS_DP15
U10
PB82A
SLVS_DN15
SLVS_DP3
V10
PB82B
SLVS_DP3
SLVS_DN3
W9
PB84A
SLVS_DN3
W10
PB84B
SLVS_DP14
SLVS_DP4
P12
PB86A
SLVS_DN14
SLVS_DN4
R12
PB86B
SLVS_DP22
R11
PB88A
SLVS_DN22
SLVS_DP5
R10
PB88B
SLVS_DP6
SLVS_DN5
Y10
PB90A
SLVS_DN6
Y11
PB90B
SLVS_DP23
SLVS_DP6
P10
PB92A
SLVS_DN23
SLVS_DN6
P11
PB92B
SLVS_DP4
V12
PB94A
SLVS_DN4
SLVS_DP7
W11
PB94B
SLVS_DP1
SLVS_DN7
V11
PB96A
SLVS_DN1
U12
PB96B
SLVS_DP0
SLVS_DP8
W13
SLVS_DN0
SLVS_DN8
W12
SLVS_DP12
U13
SLVS_DN12
SLVS_DP9
V13
SLVS_DP2
SLVS_DN9
Y12
SLVS_DN2
Y13
SLVS_DP13
SLVS_DP10
R13
SLVS_DN13
SLVS_DN10
T13
SLVS_DP5
P13
SLVS_DN5
SLVS_DP11
P14
SLVS_DP21
SLVS_DN11
M12
N12
SLVS_DN21
4
Figure A. 7. PCIE&FPC Headers (BANK4)
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
B side = Primary Component Side(TOP)
A side = Secondary Component Side(BOTTOM)
12_IN_PCIE
CN1
PRSNT1n
A1
PRSNT1#
A2
+12V
x1_PERp0
A3
+12V
x1_PERn0
A4
GND
A5
JTAG2
SMCLK
A6
JTAG3
SMDAT
A7
JTAG4
A8
JTAG5
+3.3V
PCIE_3V3
A9
+3.3V
JTAG1
SD3_TXp
A10
+3.3V
3.3Vaux
SD3_TXn
PCIE_PERSTn
A11
PERST#
WAKE#
A12
GND
RSVD
PCIE_CLKp
A13
PCIE_CLKn
REFCLK+
A14
REFCLK-
PETp0
A15
GND
PETn0
x1_PERp0
A16
PERp0
x1_PERn0
A17
PERn0
PRSNT2#
A18
GND
PCI Express x1 Edge Finger Conn.
JP10
PCIE_PERSTn
1
2
PRSNT2n
PCIE_RST
TP4
CN3
CN2
1
50
Pin1
Pin50
2
49
Pin2
Pin49
3
48
Pin3
Pin48
4
47
Pin4
Pin47
5
46
Pin5
Pin46
6
45
Pin6
Pin45
SLVS_TP2
7
44
Pin7
[8] SLVS_TP2
Pin44
8
43
Pin8
Pin43
SLVS_DP24
9
42
Pin9
[8] SLVS_DP24
Pin42
SLVS_DN24
10
41
Pin10
[8] SLVS_DN24
Pin41
11
40
Pin11
Pin40
SLVS_DP25
12
39
Pin12
[8] SLVS_DP25
Pin39
SLVS_DN25
13
38
Pin13
[8] SLVS_DN25
Pin38
14
37
Pin14
Pin37
SLVS_DP12
15
36
Pin15
Pin36
SLVS_DN12
16
35
Pin16
Pin35
17
34
Pin17
SLVS_DP13
Pin34
18
33
Pin18
Pin33
SLVS_DN13
19
32
Pin19
Pin32
20
31
Pin20
Pin31
SLVS_DP14
21
30
Pin21
Pin30
SLVS_DN14
22
29
Pin22
Pin29
23
28
Pin23
Pin28
SLVS_DP15
24
27
Pin24
Pin27
SLVS_DN15
25
26
Pin25
Pin26
26
25
Pin26
Pin25
SLVS_DP16
27
24
Pin27
SLVS_DN16
Pin24
28
23
Pin28
Pin23
29
22
Pin29
Pin22
SLVS_DP17
30
21
Pin30
SLVS_DN17
Pin21
31
20
Pin31
Pin20
32
19
Pin32
Pin19
SLVS_DP18
33
18
Pin33
Pin18
SLVS_DN18
34
17
Pin34
Pin17
35
16
Pin35
Pin16
SLVS_DP19
36
15
Pin36
Pin15
SLVS_DN19
37
14
Pin37
Pin14
38
13
Pin38
Pin13
SLVS_DP20
39
12
Pin39
Pin12
SLVS_DN20
40
11
Pin40
Pin11
41
10
Pin41
Pin10
SLVS_DP21
42
9
Pin42
Pin9
SLVS_DN21
43
8
Pin43
Pin8
44
7
Pin44
Pin7
SLVS_DP22
45
6
Pin45
Pin6
SLVS_DN22
46
5
Pin46
Pin5
47
4
Pin47
Pin4
SLVS_DP23
48
3
Pin48
Pin3
SLVS_DN23
49
2
Pin49
Pin2
50
1
Pin50
Pin1
046288050000846+
046288050000846+
3
2
X1 PCIe Board
Fingers
B1
+12V
+3.3V
B2
+12V
B3
+12V
B4
GND
TP22
B5
B6
FB19
B7
MPZ1005S121CT000
GND
PCIE_3V3
B8
B9
B10
B11
R240
B12
B13
X7
GND
x1_PETp0
B14
C299
C298
x1_PETn0
B15
10nF
100nF
10K
1
EN
B16
50V
16V
GND
Q
B17
PRSNT2n
B18
2
GND
NC
Q_N
100MHz
JP26
2
1
PRSNT1n
PRSNT
LVDS_100MHzp
EXT0_CLKp
R250
0
LVDS_100MHzn
EXT0_CLKn
R249
0
SMA0
SMA2
SD3_RXp
SD3_TXp
1
1
27G_SMA-DNI
27G_SMA-DNI
SMA1
SMA3
SD3_RXn
SD3_TXn
1
1
27G_SMA-DNI
27G_SMA-DNI
L L L a a a t t t t t t i i i c c c e e e S S S e e e m m m i i i c c c o o o n n n d d d u u u c c c t t t o o o r r r A A A p p p p p p l l l i i i c c c a a a t t t i i i o o o n n n s s s
E E E m m m a a a i i i l l l : : : t t t e e e c c c h h h s s s u u u p p p p p p o o o r r r t t t @ @ @ L L L a a a t t t t t t i i i c c c e e e s s s e e e m m m i i i . . . c c c o o o m m m
P P P h h h o o o n n n e e e ( ( ( 5 5 5 0 0 0 3 3 3 ) ) ) 2 2 2 6 6 6 8 8 8 - - - 8 8 8 0 0 0 0 0 0 1 1 1 - - - o o o r r r - - - ( ( ( 8 8 8 0 0 0 0 0 0 ) ) ) L L L A A A T T T T T T I I I C C C E E E
T T T i i i t t t l l l e e e
P P P C C C I I I e e e & & & F F F P P P C C C H H H e e e a a a d d d e e e r r r s s s ( ( ( B B B A A A N N N K K K 4 4 4 ) ) )
S S S i i i z z z e e e
P P P r r r o o o j j j e e e c c c t t t
B B B
M M M a a a c c c h h h X X X O O O 5 5 5 - - - N N N X X X 1 1 1 0 0 0 0 0 0 K K K D D D e e e v v v e e e l l l o o o p p p m m m e e e n n n t t t B B B o o o a a a r r r d d d
D D D a a a t t t e e e : : :
F F F r r r i i i d d d a a a y y y , , , F F F e e e b b b r r r u u u a a a r r r y y y 1 1 1 7 7 7 , , , 2 2 2 0 0 0 2 2 2 3 3 3
2
1
D
LVDS_100MHzp
4
LVDS_100MHzn
5
C
SMA4
EXT1_CLKp
1
27G_SMA-DNI
B
SMA5
EXT1_CLKn
1
27G_SMA-DNI
A
1 1 1 . . . 0 0 0
S S S c c c h h h e e e m m m a a a t t t i i i c c c R R R e e e v v v
B B B o o o a a a r r r d d d R R R e e e v v v
A A A
S S S h h h e e e e e e t t t
7 7 7
o o o f f f
1 1 1 1 1 1
1
FPGA-EB-02058-1.0
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