Lattice Semiconductor MachXO5T-NX-Development Board User Manual page 64

MachXO5T-NX-Development Board
Evaluation Board User Guide
ldc_set_location -site {Y8} [get_ports {slvs_data[7]}]
ldc_set_location -site {Y6} [get_ports {slvs_data[8]}]
ldc_set_location -site {U7} [get_ports {slvs_data[9]}]
ldc_set_location -site {T7} [get_ports {slvs_data[10]}]
ldc_set_location -site {R8} [get_ports {slvs_data[11]}]
ldc_set_location -site {U13} [get_ports {slvs_data[12]}]
ldc_set_location -site {R13} [get_ports {slvs_data[13]}]
ldc_set_location -site {P12} [get_ports {slvs_data[14]}]
ldc_set_location -site {U10} [get_ports {slvs_data[15]}]
ldc_set_location -site {U9} [get_ports {slvs_data[16]}]
ldc_set_location -site {R9} [get_ports {slvs_data[17]}]
ldc_set_location -site {W7} [get_ports {slvs_data[18]}]
ldc_set_location -site {N9} [get_ports {slvs_data[19]}]
ldc_set_location -site {N7} [get_ports {slvs_data[20]}]
ldc_set_location -site {M12} [get_ports {slvs_data[21]}]
ldc_set_location -site {R11} [get_ports {slvs_data[22]}]
ldc_set_location -site {P10} [get_ports {slvs_data[23]}]
ldc_set_location -site {Y2} [get_ports {slvs_data[24]}]
ldc_set_location -site {V1} [get_ports {slvs_data[25]}]
ldc_set_location -site {W4} [get_ports {slvs_data[26]}]
ldc_set_location -site {W5} [get_ports {slvs_data[27]}]
//LPDDR4
# DQS GROUP 0
ldc_set_location -site {N18} [get_ports {ddr_dq_io[0]}]
ldc_set_location -site {N20} [get_ports {ddr_dq_io[1]}]
ldc_set_location -site {P18} [get_ports {ddr_dq_io[2]}]
ldc_set_location -site {P17} [get_ports {ddr_dq_io[3]}]
ldc_set_location -site {P16} [get_ports {ddr_dq_io[4]}]
ldc_set_location -site {N19} [get_ports {ddr_dq_io[5]}]
ldc_set_location -site {M17} [get_ports {ddr_dq_io[6]}]
ldc_set_location -site {M16} [get_ports {ddr_dq_io[7]}]
ldc_set_location -site {P19} [get_ports {ddr_dqs_io[0]}]
ldc_set_location -site {N17} [get_ports {ddr_dmi_io[0]}]
# DQS GROUP 1
ldc_set_location -site {R15} [get_ports {ddr_dq_io[8]}]
ldc_set_location -site {T14} [get_ports {ddr_dq_io[9]}]
ldc_set_location -site {R14} [get_ports {ddr_dq_io[10]}]
ldc_set_location -site {T15} [get_ports {ddr_dq_io[11]}]
ldc_set_location -site {V14} [get_ports {ddr_dq_io[12]}]
ldc_set_location -site {W14} [get_ports {ddr_dq_io[13]}]
ldc_set_location -site {V15} [get_ports {ddr_dq_io[14]}]
ldc_set_location -site {U14} [get_ports {ddr_dq_io[15]}]
ldc_set_location -site {Y15} [get_ports {ddr_dqs_io[1]}]
ldc_set_location -site {U15} [get_ports {ddr_dmi_io[1]}]
ldc_set_port -iobuf {IO_TYPE=LVSTL_I TERMINATION=40} [get_ports {ddr_dmi_io[*]}]
ldc_set_port -iobuf {IO_TYPE=LVSTL_I TERMINATION=40} [get_ports {ddr_dq_io[*]}]
ldc_set_port -iobuf {IO_TYPE=LVSTLD_I TERMINATION=40} [get_ports
{ddr_dqs_io[*]}]
# CK, CKE, CS, CA
ldc_set_location -site {R19} [get_ports {ddr_ck_o[0]}]
ldc_set_location -site {W20} [get_ports {ddr_cke_o[0]}]
ldc_set_location -site {W18} [get_ports {ddr_cs_o[0]}]
ldc_set_location -site {W19} [get_ports {ddr_ca_o[0]}]
ldc_set_location -site {V18} [get_ports {ddr_ca_o[1]}]
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64 FPGA-EB-02058-1.0