MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
6. SGMII Ethernet Connections
This section describes the MachXO5-NX Development Board SGMII application for Ethernet connections.
Table 6.1. SGMII Ethernet PHY Connections
U7 Pin Number
U7 Signal Name
1
2
3
VDDA2P5
4
5
6
7
8
9
VDDA2P5
10
11
12
13
VDDA1P8
14
15
16
17
18
CLK_OUT
19
20
JTAG_CLK
21
JTAG_TDO
22
JTAG_TMS
23
JTAG_TDI
24
25
26
27
TX_D1/SGMII_SIP
28
TX_D0/SGMII_SIN
29
GTX_CLK
30
31
32
33
RX_D0/SGMII_COP
34
RX_D1/SGMII_CON
35
RX_D2/SGMII_SOP
36
RX_D3/SGMII_SON
37
38
39
40
41
42
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18
Net Name
TD_P_A
SGMII_MD0_P
TD_M_A
SGMII_MD0_N
+2.5V
TD_P_B
SGMII_MD1_P
TD_M_B
SGMII_MD1_N
VDD1P0
VCCA_1V_PHY
TD_P_C
SGMII_MD2_P
TD_M_C
SGMII_MD2_N
+2.5V
TD_P_D
SGMII_MD3_P
TD_M_D
SGMII_MD3_P
RBIAS
—
SGMII_PHY_D1V8
XO
SGMII_XO
XI
SGMII_XI
MDC
SGMII_MDIO_CLK
MDIO
SGMII_MDIO_DATA
SGMII_CLK_OUT
VDDIO
SGMII_VDDIO
—
—
—
—
VDD1P0
VCCA_1V_PHY
TX_D3
—
TX_D2
—
SGMII_PHY_SIP
SGMII_PHY_SIN
—
VDDIO
SGMII_VDDIO
VDD1P0
VCCA_1V_PHY
RX_CLK
—
SGMII_PHY_COP
SGMII_PHY_CON
SGMII_PHY_SOP
SGMII_PHY_SON
TX_CTRL
—
RX_CTRL
—
GPIO_0
—
GPIO_1
—
VDDIO
SGMII_VDDIO
VDD1P0
VCCA_1V_PHY
MachXO5-25 Ball Location
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1
U2
T7
—
—
—
—
—
—
—
—
N8
P8
—
—
—
—
U9
V9
N9
P9
—
—
—
—
—
—
Application Notes
To RJ45
To RJ45
2.5 V Power
To RJ45
To RJ45
1.0 V Power
To RJ45
To RJ45
2.5 V Power
To RJ45
To RJ45
Pull down to GND
1.8 V Power
25 MHz Crystal Output
25 MHz Crystal Input
Optional pull up to
VDDIO
Pull up to VDDIO
With 22 Ω debounce
resistor
VCCIO7 selectable
Pull down to GND
Pull up to VDDIO
Pull up to VDDIO
Pull up to VDDIO
1.0 V Power
Pull down to GND
Pull down to GND
0.1 µF AC coupling
0.1 µF AC coupling
Pull down to GND
VCCIO7 selectable
1.0 V Power
—
0.1 µF AC coupling
0.1 µF AC coupling
0.1 µF AC coupling
0.1 µF AC coupling
Pull down to GND
—
Pull down to GND
Pull down to GND
VCCIO7 selectable
1.0 V Power
FPGA-EB-02052-0.90