MachXO5T-NX-Development Board
Evaluation Board User Guide
Figures
Figure 2.1. Board Power Supply.......................................................................................................................................... 10
2
C Programming Architecture ................................................................................................................ 12
Figure 3.4. JTAG Test Header .............................................................................................................................................. 13
2
C Programming Mode .................................................................................................................................... 14
Figure 6.1. SGMII ×2 Interfacing ......................................................................................................................................... 19
Figure 8.3. SMA Clock Input ................................................................................................................................................ 23
Figure A. 1. Title Page ......................................................................................................................................................... 44
Figure A. 3. USB to Hard JTAG I/F ....................................................................................................................................... 46
Figure A. 6. LPDDR4 (BANK3) .............................................................................................................................................. 49
Figure A. 8. GBE and RJ45 (BANK5) ..................................................................................................................................... 51
Figure A. 10. Power Rails .................................................................................................................................................... 53
Figure A. 11. Power Regulators .......................................................................................................................................... 54
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4
FPGA-EB-02058-1.0
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