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MachXO5T-NX-Development Board
Evaluation Board User Guide
Figures
Figure 1.1. Top View of MachXO5T-NX Development Board ............................................................................................... 7
Figure 1.2. Bottom View of MachXO5T-NX Development Board ......................................................................................... 8
Figure 2.1. Board Power Supply.......................................................................................................................................... 10
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C Programming Architecture ................................................................................................................ 12
Figure 3.2. Radiant Programmer Detect Dual Ports ........................................................................................................... 12
Figure 3.3. Level Shift for JTAG Download Interface .......................................................................................................... 13
Figure 3.4. JTAG Test Header .............................................................................................................................................. 13
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C Programming Mode .................................................................................................................................... 14
Figure 4.1. JTAG/UART User Interfacing ............................................................................................................................. 16
Figure 5.1. Onboard Clock Resources ................................................................................................................................. 18
Figure 6.1. SGMII ×2 Interfacing ......................................................................................................................................... 19
Figure 7.1. Top Side of PCIe Edge Connector...................................................................................................................... 21
Figure 8.1. SMA Interfacing for x1 Serdes RX and TX ......................................................................................................... 22
Figure 8.2. SMA Interfacing for x1 SerDes Rx and Tx .......................................................................................................... 22
Figure 8.3. SMA Clock Input ................................................................................................................................................ 23
Figure 10.1. Radiant Software - Open Project Dialog Box ................................................................................................. 25
Figure 10.2. Radiant Software - Process Toolbar Initial State ............................................................................................ 25
Figure 10.3. Radiant Software - State of the Processes Toolbar Completion .................................................................... 26
Figure 11.1. Radiant Software - Radiant Programmer ....................................................................................................... 27
Figure 11.2. Radiant Programmer - Initial Opened ............................................................................................................ 28
Figure 11.3. Radiant Programmer - Scan Device ............................................................................................................... 28
Figure 11.4. Radiant Programmer - Device Detected ........................................................................................................ 29
Figure 11.5. Radiant Programmer - Select Target Memory for Device Properties ............................................................ 29
Figure 11.6. Radiant Programmer - Device Properties for FLASH Configuration Memory ................................................ 30
Figure 11.7. Radiant Programmer - Ready for Flash Programming ................................................................................... 31
Figure 11.8. Radiant Programmer - Flash Programming Successful .................................................................................. 31
Figure 12.1. Circuit Design for ADC0 ................................................................................................................................... 39
Figure 12.2. Circuit Design for ADC1 ................................................................................................................................... 39
Figure 12.3. Trimmer Wiper Description ............................................................................................................................ 39
Figure 13.1. Eight-Position DIP Switch Circuits ................................................................................................................... 40
Figure 13.2. Eight-position DIP Switch ................................................................................................................................ 40
Figure A. 1. Title Page ......................................................................................................................................................... 44
Figure A. 2. Block Diagram and Power Tree ....................................................................................................................... 45
Figure A. 3. USB to Hard JTAG I/F ....................................................................................................................................... 46
Figure A. 4. USB to Soft JTAG I/F (BANK0) .......................................................................................................................... 47
Figure A. 5. PMOD0/Versa Connector (BANK1/2) .............................................................................................................. 48
Figure A. 6. LPDDR4 (BANK3) .............................................................................................................................................. 49
Figure A. 7. PCIE&FPC Headers (BANK4) ............................................................................................................................ 50
Figure A. 8. GBE and RJ45 (BANK5) ..................................................................................................................................... 51
Figure A. 9. Multiple Headers (BANK6/7) ........................................................................................................................... 52
Figure A. 10. Power Rails .................................................................................................................................................... 53
Figure A. 11. Power Regulators .......................................................................................................................................... 54
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-EB-02058-1.0
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