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MachXO5T-NX-Development Board
Evaluation Board User Guide
Table 6.2. SGMII Ethernet PHY0 Strapping Configuration
Configuration Item
U6 Pin Number
Description
37
PS_PHY_MADDR(0)
35
PS_PHY_MADDR(1)
34
PS_PHY_MADDR(2)
3
PS_PHY_MADDR(3)
2
PS_PHY_MADDR(4)
12
PS_MINT_POL
18
PS_RJ45_TAP
19
PS_MDIO_VOLTAGE
Table 6.3. SGMII Ethernet PHY1 Strapping Configuration
Configuration Item
U7 Pin Number
Description
37
PS_PHY_MADDR(0)
35
PS_PHY_MADDR(1)
34
PS_PHY_MADDR(2)
3
PS_PHY_MADDR(3)
2
PS_PHY_MADDR(4)
12
PS_MINT_POL
18
PS_RJ45_TAP
19
PS_MDIO_VOLTAGE
MachXO5T-NX Development Board provides two options to supply the VDD power of PHY devices, as shown in
Table
6.4. One option is to supply the VDD with on-board 1.0 V regulator. The other option needs additional power
from the on-board 3.3 V LDO and converts to 1.0 V output by the internal regulator of PHY devices. It is recommended
to use the first option to improve the power efficiency and off load the 3.3V LDO on this board.
Table 6.4. PHY device VDD Power Supply Options
PHY VDD
U6
U7
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20
Logic Value in Default
Logic Value in Default
Jumper
Supply from On-board Regulator
J26
Pin 2-3 (U12)
J28
Pin 2-3 (U12)
1K Pull up Resistor
0
R182 (DNI)
0
R178 (DNI)
0
R179 (DNI)
0
R180 (DNI)
0
R181 (DNI)
0
R183 (DNI)
0
R184 (DNI)
0
NA
1K Pull up Resistor
0
R224(DNI)
0
R220(DNI)
0
R221(DNI)
0
R222(DNI)
0
R223(DNI)
0
R225(DNI)
0
R226(DNI)
0
—
1K Pull down Resistor
R172
R173
R174
R175
R176
R171
R170
R177
1K Pull down Resistor
R215
R216
R217
R218
R219
R214
R213
R202
Supply from in-chip Regulator
Pin 1-2 (U6)
Pin 1-2 (U7)
FPGA-EB-02058-1.0
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