Headers And Test Connections; Versa Headers; Table 12.1. Versa J8 Header Pin Connections - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

MachXO5T-NX-Development Board
Evaluation Board User Guide

12. Headers and Test Connections

This section describes the MachXO5T-NX Development Board headers and test connections.

12.1. Versa Headers

The board provides two headers, J8 and J9, for expansion purpose.

Table 12.1. Versa J8 Header Pin Connections

J8 Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
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32
Net Name
GND
NC
EXPCON_2V5*
EXPCON_IO29
EXPCON_IO30
EXPCON_IO31
EXPCON_IO32
EXPCON_IO33
EXPCON_IO34
EXPCON_IO35
EXPCON_IO36
EXPCON_IO37
EXPCON_IO38
EXPCON_IO39
EXPCON_IO40
EXPCON_IO41
EXPCON_IO42
EXPCON_IO43
EXPCON_IO44
EXPCON_IO45
5VIN*
GND
EXPCON_2V5*
GND
+3.3V
GND
+3.3V
GND
EXPCON_OSC
GND
EXPCON_CLKIN
GND
EXPCON_CLKOUT
GND
EXPCON_3V3**
GND
EXPCON_3V3**
GND
EXPCON_3V3**
GND
LFMXO5-100T Ball Location
—
—
—
J10
J11
K10
J17
J12
H20
H19
K11
J19
J14
J13
K16
J15
K14
K15
K12
K13
—
—
—
—
—
—
—
—
J16
—
J18
—
J20
—
—
—
—
—
—
—
FPGA-EB-02058-1.0