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Lattice Semiconductor
Table 17. Logic Analyzer Connections (Continued)
MICTOR Pin
27
29
31
33
35
37
RS-232 Interface
J36
(see Appendix A, Figures 5 and 16)
A simple 2x5 Header provides a connection to create a RS-232 serial communications port. The connection
includes the proper level shift needed to connect to a serial port of a PC. The RX and TX pins are connected to the
FPGA.
Table 18. RS-232 TX/RX
LCD Interface
J41
(see Appendix A, Figures 5 and 16)
A 2x8 Header provides a connection to 16-character x 2 line LCD modules such as Varitronix VDM16265. A ribbon
cable connection will allow attachment to the connector. The board includes two variable resistors for LCD adjust-
ments. VR1 adjusts the backlight and VR2 provides contrast adjustment. A user design must be included in the
FPGA to drive this feature.
2
I
C Interface
(see Appendix A, Figures 5 and 16)
2
I
C interface is supplied between the FPGA and two ICs. This interface is used to access a Maxim temperature
sensing device as well as a EEPROM. The temperature-sensing device is also connected back to the FPGA via the
PTEMP pins to monitor device temperature.
2
Table 19. I
C Interface
Ethernet Interface
(see Appendix A, Figures 5 and 13)
Interconnection to Base 10/100/1000 Ethernet protocols is supported via a RJ-45 connection (J35). This connec-
tion is electrically interfaced to the FPGA through a tri-speed PHY device. Use of this interface requires a MAC
Signal
900-Ball fpBGA
LA_10
AK6
LA_11
AK7
LA_12
AF14
LA_13
AF15
LA_14
AJ11
LA_15
AG13
Signal
RS232-RXD
RS232-TXD
Signal
900-Ball fpBGA
SCL
SDA
MICTOR Pin
28
30
32
34
36
38
900-Ball fpBGA
F13
F12
Buffer Type
B11
LVCMOS25 or LVTTL33
B12
LVCMOS25 or LVTTL33
13
LatticeSC PCI Express x1
Evaluation Board User's Guide
Signal
900-Ball fpBGA
LA_26
LA_27
LA_28
LA_29
LA_30
LA_31
Buffer Type
LVCMOS25
LVCMOS25
AJ13
AD15
AE15
AK12
AK13
AJ14
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