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Lattice Semiconductor
Table 26. DDR2 Interface to SODIMM Socket (Continued)
Description
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_A13
DDR_BA0
DDR_BA1
DDR_BA2
DDR2_CK0_P
DDR2_CK0_N
DDR2_CK1_P
DDR2_CK1_N
DDR2_CKE0
DDR2_CKE1
DDR2_S0_N
DDR2_S1_N
DDR2_RAS_N
DDR2_CAS_N
DDR2_WE_N
DDR2_ODT0
DDR2_ODT1
DDR2_SDA
DDR2_SCL
Ethernet PHY
In the upper middle portion of the board is U11, a National Semiconductor Gigabit Ethernet PHY (DP83865). The
LatticeXP2 FPGA interacts with the PHY over a Media Independent Interface (MII). The PHY is connected to an
RJ45 connector J43 on the Media Dependent Interface (MDI). The RJ45 connector J43 has built in magnetics and
spark-gap capacitor.
The PHY is available on the board in order to demonstrate the Lattice Ethernet Media Access (MAC) IP core. How-
ever, it is also possible to use the PHY to evaluate a custom MAC solution.
Refer to the schematic and the National Semiconductor DP83865 Data Sheet for detailed information about the
operation of the Ethernet PHY interface on this device. Refer to Table 27 for a description of the Ethernet PHY con-
nections.
LatticeXP2 I/O
R16
T17
Y20
Y19
W22
G15
G16
F17
P20
P22
F18
G17
H18
B21
C21
J19
C20
J18
H16
K16
L18
L19
P18
N18
AA2
Y2
18
LatticeXP2 Advanced
Evaluation Board User's Guide
sysIO Bank
3
3
3
3
3
2
2
2
3
3
2
2
2
2
2
2
2
2
2
2
2
2
3
3
0
0
J36
94
92
93
91
105
90
89
116
107
106
85
30
32
164
166
79
80
110
115
108
113
109
114
119
195
197
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