Lfmxo5-100T Clock Sources; Figure 5.1. Onboard Clock Resources; Table 5.1. Input Clock Options - Lattice Semiconductor MachXO5T-NX-Development Board User Manual

MachXO5T-NX-Development Board
Evaluation Board User Guide

5. LFMXO5-100T Clock Sources

The MachXO5T-NX Development Board has multiple external clock options for the LFMXO5-100T applications as shown
in Figure 5.1.
•
12 MHz from U1 (FTDI)
•
27 MHz from ×4 (OSC MEM)
•
External clock source from J10 (SMA)
•
Differential 100 MHz from ×7
•
Differential 100 MHz from ×8
•
Differential 125 MHz from ×9
•
Differential external clock source from SMA4 and SMA5 (SMA pair)
x7
x8
x9
SMA4/5
You need take care 12 MHz clocks from the FT2232H FTDI U1 device are not always on without some hardware
configuration. SMA clocks need source from external boards. Refer to
conditions.

Table 5.1. Input Clock Options

Clock
Net Name
Frequency
12 MHz EXPCON_OSC
27 MHz 27M_OSC_IN
EXT_CLK OSC_IN
EXT0_CLKp/
100 MHz
EXT0_CLKn
LVSTLD_100MHzp/
100 MHz
LVSTLD_100MHzn
LVDS_125MHzp/
125 MHz
LVDS_125MHzn
EXT1_CLKp/EXT1_
SMA_CLK
CLKn
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18
100 MHz
100 MHz
125 MHz
EXT1_CLK

Figure 5.1. Onboard Clock Resources

LFMXO5-
Clock
100T Ball
Source
Location
J16 U1
C2 X4
A17 J10
C11/C12 X7
U19/U20 X8
R3/P3 X9
SMA4/
B13/C13
SMA5
J8
EXPCON_OSC
12 MHz
R159
27 MHz
EXT_CLK
Table 5.1 for those clock utilization and enable
IO Type Enable Conditions
Need add R159 and JP11. USB header J11
LVCMOS33
connected with power on.
Always on. Use J25 to disable or control clock
LVCMOS33
output.
LVCMOS33 or Need add J10 SMA. Connect to external clock
LVCOMS25 generator through SMA cable.
Always on. Dedicated reference clock for PCS.
LVDS Refer to the SerDes/PCS User Guide FPGA-TN-
02245 for details.
Always on. Generated by the HSCL clock and AC
LVSTLD
coupled to the 1.1 V I/O bank for LPDDR4.
Always on. Dedicated reference clock for PCS.
LVDS Refer to the CertusPro-NX SerDes/PCS User Guide
(FPGA-TN-02245)
Need add SMA4 and SMA5. Connect to external
LVDS
differential clock generator through SMA cables.
J11
USB
JP11
U1
x4
J10
for details.
FPGA-EB-02058-1.0