Lattice Semiconductor MachXO5T-NX-Development Board User Manual page 5

MachXO5T-NX-Development Board
Evaluation Board User Guide
Tables
Table 2.1. Onboard Major Power Rails ............................................................................................................................... 11
Table 2.2. LFMXO5-100T IO Bank Power Rails Stuff ........................................................................................................... 11
Table 2.3. LFMXO5-100T Major Power Rails Stuff .............................................................................................................. 11
Table 3.1. Config JTAG Connections ................................................................................................................................... 14
Table 3.2. Other Config JTAG Control Signals ..................................................................................................................... 14
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Table 3.3. Download I C Connections ................................................................................................................................. 15
Table 4.1. Soft JTAG Connections ....................................................................................................................................... 16
Table 4.2. Soft UART Connections ...................................................................................................................................... 17
Table 5.1. Input Clock Options ............................................................................................................................................ 18
Table 6.1. SGMII Ethernet PHY Interfacing ......................................................................................................................... 19
Table 6.2. SGMII Ethernet PHY0 Strapping Configuration .................................................................................................. 20
Table 6.3. SGMII Ethernet PHY1 Strapping Configuration .................................................................................................. 20
Table 6.4. PHY device VDD Power Supply Options ............................................................................................................. 20
Table 7.1. Gold Finger Pin Connections .............................................................................................................................. 21
Table 8.1. Connections for SMA Serdes signal pair ............................................................................................................ 22
Table 8.2. Connections for External SMA Reference Clock ................................................................................................ 22
Table 8.3. Single-end External SMA Clock .......................................................................................................................... 23
Table 9.1. LPDDR4 Memory Controller Interconnections .................................................................................................. 24
Table 12.1. Versa J8 Header Pin Connections..................................................................................................................... 32
Table 12.2. Versa J9 Header Pin Connections..................................................................................................................... 33
Table 12.3. Arduino J2 Pin Connections ............................................................................................................................. 34
Table 12.4. Arduino J3 Pin Connections ............................................................................................................................. 34
Table 12.5. Arduino J4 Pin Connections ............................................................................................................................. 34
Table 12.6. Arduino J5 Pin Connections ............................................................................................................................. 35
Table 12.7. FPC Header Pin Connections ............................................................................................................................ 35
Table 12.8. Aardvark J7 Header Pin Connections ............................................................................................................... 36
Table 12.9. Raspberry Pi J6 Header Pin Connections ......................................................................................................... 37
Table 12.10. J15 Header Pin Connections .......................................................................................................................... 37
Table 12.11. J16 Header Pin Connections .......................................................................................................................... 38
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Table 12.12. I C Connections .............................................................................................................................................. 38
Table 13.1. Four-Position DIP Switch Signals ...................................................................................................................... 40
Table 13.2. Push Button Switch Signals .............................................................................................................................. 41
Table 13.3. LED Signals ....................................................................................................................................................... 41
Table 16.1 Ordering Information ........................................................................................................................................ 42
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FPGA-EB-02058-1.0 5