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MachXO5T-NX-Development Board
Evaluation Board User Guide
5
VCCIO6
U3G
L4
VCCIO6
PL40A
PL40B
C43
PL42A/PCLKT6_0
D
PL42B
0.1uF
PL44A/PCLKT6_1
PL44B
PL46A/PCLKT6_2
PL46B
PL47A
PL47B
PL49A
PL49B
PL51A
PL51B
PL53A
PL53B
PL55A
PL55B
VCCIO6
PL56A
PL56B
PL58A
C42
PL58B
PL60A
10uF
PL60B
PL62A
PL62B
C
PL64A
PL64B
PL65A
PL65B
PL67A
PL67B
LFMXO5-100-BBG400
VCCIO7
U3H
G5
VCCIO7
PL3A/ULC_GPLL0T_IN
F4
VCCIO7
C50
C51
0.1uF
0.1uF
B
VCCIO7
C49
10uF
PL28A/PCLKT7_2
PL29A/PCLKT7_1
PL31A/PCLKT7_0
A
LFMXO5-100-BBG400
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
4
AR_IO4
J7
AR_IO2
J6
AR_IO7
K8
AR_IO5
VCCIO6
J8
AR_IO9
K2
AR_IO8
K3
AR_IO0
K4
R46
AR_IO1
K5
K6
SW2
SW2
[7]
AR_IO3
K7
AR_RESET
J9
4.7k
SW2
AR_IO6
H9
AR_SS_IO10
K1
SW2
AR_MISO_IO12
L1
AR_SCK_IO13
L2
PB1
C17
AR_MOSI_IO11
L3
AR_AREF
L6
100nF
AR_IO14
L7
AR_AD0
M1
AR_AD1
M2
AR_AD2
M3
AR_AD3
M4
AR_AD4
M5
AR_AD5
M6
AK_SCL
M7
0
DNI
R60
SCL0
SCL0 [3,9]
AK_SDA
M8
0
DNI
R59
SDA0
SDA0 [3,9]
AK_MISO
N1
AK_SCLK
N2
AK_SS
N3
AK_MOSI
N4
AR_SDA
N5
0
DNI
R44
SDA0
AR_SCL
N6
0
DNI
R45
SCL0
NOTE : 0 OHM RESISTOR SHUOULD BE PLACED
NEAR U3
27M_OSC_IN
27M_OSC_OUT
C2
0
R72
27M_OSC_CTL
D2
PL3B
RASP_ID_SC
E1
0
DNI
R85
SCL0
PL4A
RASP_ID_SD
D1
0
DNI
R87
SDA0
PL4B
RASP_IO24
E3
PL6A
RASP_IO23
E4
PL6B
RASP_IO22
E5
PL8A
RASP_IO09
E2
PL8B
RASP_IO27
E6
PL10A
RASP_IO17
E7
PL10B
RASP_IO12
+3.3V_RASP
F5
PL13A
RASP_IO03
F6
0
DNI
R96
SCL0
PL13B
RASP_IO02
E8
0
DNI
R84
SDA0
PL15A
RASP_IO10
RASP_IO02
F7
PL15B
RASP_IO25
RASP_IO03
F3
C30
PL17A
RASP_IO11
RASP_IO04
F2
PL17B
RASP_IO07
G3
100nF
PL19A
RASP_IO06
RASP_IO17
G2
PL19B
RASP_IO13
RASP_IO27
G6
PL20A
RASP_IO18
RASP_IO22
G7
PL20B
RASP_IO14
G8
PL22A
RASP_IO15
RASP_IO10
F8
PL22B
RASP_IO05
RASP_IO09
G1
PL24A
RASP_IO08
RASP_IO11
F1
PL24B
RASP_IO04
G9
PL26A
RASP_IO21
RASP_ID_SD
H8
PL26B
RASP_IO26
RASP_IO05
H6
RASP_IO20
RASP_IO06
H7
PL28B
RASP_IO16
RASP_IO13
H5
RASP_IO19
RASP_IO19
H4
PL29B
PMOD1_4
RASP_IO26
H3
PMOD1_8
H2
PL31B
PMOD1_3
H1
PL33A
PMOD1_2
J1
PL33B
PMOD1_7
J2
PL35A
PMOD1_6
J3
PL35B
PMOD1_1
J4
PL38A
PMOD1_5
J5
PL38B
4
Figure A. 9. Multiple Headers (BANK6/7)
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
ARDUINO Connectors
NOTE: Those Headers only support 3.3V IOs, never apply more than 3.3V to its inputs or outputs.
Care must be taken when connecting sensors and actuators to assure that this is never exceeded.
Connecting higher voltages, like the 5V commonly used with some Arduino boards, will damage this board.
AK_SCLK
0
DNI
R86
UTCK
UTCK [4]
AK_MOSI
0
DNI
R88
UTDI
UTDI [4]
AK_MISO
0
DNI
R92
UTDO
UTDO [4]
AK_SS
UTMS
0
DNI
R94
UTMS [4]
J16
PMOD1_1
PMOD1_5
1
7
PMOD1_2
PMOD1_6
2
8
PMOD1_3
PMOD1_7
3
9
PMOD1_4
PMOD1_8
4
10
VCCIO7
5
11
6
12
PMOD 2x6
C123
100nF
AARDVARK
Connector
+5.0V
J7
AK_SCL
1
2
1
2
AK_SDA
+5V_I2C
3
4
0
DNI
R78
3
4
AK_MISO
+5V_SPI
5
6
0
DNI
R79
5
6
AK_SCLK
AK_MOSI
7
8
7
8
AK_SS
9
10
9
10
HEADER 5X2
DNI
AARDVARK
+5.0V
JP7
2
1
J6
RASP_5V
1
2
1
2
RASP5V
3
4
3
4
5
6
5
6
RASP_IO14
7
8
C29
7
8
RASP_IO15
9
10
9
10
RASP_IO18
11
12
100nF
11
12
13
14
13
14
RASP_IO23
15
16
15
16
RASP_IO24
17
18
17
18
19
20
19
20
RASP_IO25
21
22
21
22
RASP_IO08
23
24
23
24
RASP_IO07
25
26
25
26
RASP_ID_SC
27
28
27
28
29
30
29
30
RASP_IO12
31
32
31
32
33
34
33
34
RASP_IO16
35
36
35
36
RASP_IO20
37
38
37
38
RASP_IO21
39
40
39
40
Receptacle 20X2
DNI
Raspberry PI Connector
3
2
J3
J5
AR_IO0
AR_AD5
1
6
IO0/RXD
AD5/SCL
AR_IO1
AR_AD4
2
5
IO1/TXD
AD4/SDA
AR_IO2
AR_AD3
3
4
IO2
AD3
AR_IO3
AR_AD2
4
3
IO3/PWM
AD2
AR_IO4
AR_AD1
5
2
AR_IO5
IO4
AR_AD0
AD1
6
1
IO5/PWM
AD0
AR_IO6
7
IO6/PWM
AR_IO7
8
Header 1x6
IO7
DNI
Header 1x8
+3.3V_AR +5.0V
+12V
DNI
J2
AR_IO8
1
IO8
AR_IO9
2
JP6
J4
IO9/PWM
AR_SS_IO10
3
AR5V
8
SS/PWM
VIN
AR_MOSI_IO11
4
7
MOSI/PWM
GND2
AR_MISO_IO12
5
6
AR_SCK_IO13
MISO
AR_5V
GND1
6
5
SCK
5V0
7
4
GND
3V3
AR_AREF
AR_RESET
0
DNI
R43
8
3
AREF
RESET
AR_SDA
9
2
AD4/SDA
IOREF
AR_SCL
AR_IO14
10
1
AD5/SCL
N/A
Header 1x10
Header 1x8
DNI
DNI
J25 default open
VCCIO7
1-2 leave X4 controlled by FPGA
2-3 disable X4 output
FB7
27M_OSC_CTL
MPZ1005S121CT000
27M_OSC_EN
OSCILLATOR
R28
100K
X4
27M_OSC_EN
4
1
VDD
STDBY#
C34
27M_OSC_OUT
2
3
100nF
GND
OUT
27MHZ
L L L a a a t t t t t t i i i c c c e e e S S S e e e m m m i i i c c c o o o n n n d d d u u u c c c t t t o o o r r r A A A p p p p p p l l l i i i c c c a a a t t t i i i o o o n n n s s s
E E E m m m a a a i i i l l l : : : t t t e e e c c c h h h s s s u u u p p p p p p o o o r r r t t t @ @ @ L L L a a a t t t t t t i i i c c c e e e s s s e e e m m m i i i . . . c c c o o o m m m
P P P h h h o o o n n n e e e ( ( ( 5 5 5 0 0 0 3 3 3 ) ) ) 2 2 2 6 6 6 8 8 8 - - - 8 8 8 0 0 0 0 0 0 1 1 1 - - - o o o r r r - - - ( ( ( 8 8 8 0 0 0 0 0 0 ) ) ) L L L A A A T T T T T T I I I C C C E E E
T T T i i i t t t l l l e e e
M M M u u u l l l t t t i i i p p p l l l e e e H H H e e e a a a d d d e e e r r r s s s ( ( ( B B B A A A N N N K K K 6 6 6 / / / 7 7 7 ) ) )
S S S i i i z z z e e e
P P P r r r o o o j j j e e e c c c t t t
B B B
M M M a a a c c c h h h X X X O O O 5 5 5 - - - N N N X X X 1 1 1 0 0 0 0 0 0 K K K D D D e e e v v v e e e l l l o o o p p p m m m e e e n n n t t t B B B o o o a a a r r r d d d
D D D a a a t t t e e e : : :
F F F r r r i i i d d d a a a y y y , , , F F F e e e b b b r r r u u u a a a r r r y y y 1 1 1 7 7 7 , , , 2 2 2 0 0 0 2 2 2 3 3 3
2
1
D
C
J25
1
2
3
X4_CTL
B
A
1 1 1 . . . 0 0 0
S S S c c c h h h e e e m m m a a a t t t i i i c c c R R R e e e v v v
B B B o o o a a a r r r d d d R R R e e e v v v
A A A
S S S h h h e e e e e e t t t
9 9 9
o o o f f f
1 1 1 1 1 1
1
FPGA-EB-02058-1.0
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