Table of Contents
Advertisement
Detailed I/O Memory Maps
The following tables provide detailed memory maps for the VMEchip2,
MCchip, the MCECC memory controller chip, the Zilog Z85230, the Intel
82596CA controller, the NCR 53C710 controller, the IPIC chip, and the
MK48T08 BBRAM/TOD Clock.
Tables X-X - XX define the programming model for the Local Control and
Status Registers (LCSR) in the VMEchip2. The local bus map decoder for
the LCSR is included in the VMEchip2. The base address of the LCSR is
$FFF40000 and the registers are 32-bits wide. Byte, two-byte, and
four-byte read operations are permitted: however, byte and two-byte write
operations are not permitted. Byte and two-byte write operations return a
TEA signal to the local bus. Read-modify-write operations should be used
to modify a byte or a two-byte of a register.
Each register definition includes a table with 5 lines:
http://www.mcg.mot.com/literature
Line 1 is the base address of the register and the number of bits
defined in the table.
Line 2 shows the bits defined by this table.
Line 3 defines the name of the register or the name of the bits in the
register.
Line 4 defines the operations possible on the register bits as follows:
R
This bit is a read-only status bit.
R/W
This bit is readable and writable.
W/AC This bit can be set and it is automatically cleared. This bit can
also be read.
C
Writing a one to this bit clears this bit or another bit. This bit
reads zero.
S
Writing a one to this bit sets this bit or another bit. This bit
reads zero.
Line 5 defines the state of the bit following a reset as follows:
P
The bit is affected by powerup reset.
S
The bit is affected by SYSRESET.
L
The bit is affected by local reset.
X
The bit is not affected by reset.
Memory Maps
1
1-31
Advertisement
Table of Contents
