Integrated Memory Controller States; Dmi2 / Pci Express* Link States; Dmi2/Pci Express* Link States; System Memory Power States - Intel BX80619I73960X Datasheet

Power Management
4.1.3

Integrated Memory Controller States

Table 4-4.

System Memory Power States

Power Up/Normal Operation
CKE Power Down
Self-Refresh
4.1.4

DMI2 / PCI Express* Link States

Table 4-5.

DMI2/PCI Express* Link States

State
L0
1
L1
Notes:
1. L1 is only supported when the DMI2/PCI Express port is operating as a PCI Express port.
Datasheet, Volume 1
State
CKE asserted. Active Mode, highest power consumption.
Opportunistic, per rank control after idle time:
• Active Power Down (APD) (default mode)
— CKE de-asserted. Power savings in this mode, relative to active idle
• Pre-charge Power Down Fast Exit (PPDF)
— CKE de-asserted. DLL-On. Also known as Fast CKE. Power savings in
• Pre-charge Power Down Slow Exit (PPDS)
— CKE de-asserted. DLL-Off. Also known as Slow CKE. Power savings in
• Register CKE Power Down
— IBT-ON mode: Both CKE's are de-asserted, the Input Buffer
— IBT-OFF mode: Both CKE's are de-asserted, the Input Buffer
CKE de-asserted. In this mode, no transactions are executed and the system
memory consumes the minimum possible power. Self refresh modes apply to
all memory channels for the processor.
• IO-MDLL Off: Option that sets the IO master DLL off when self refresh
occurs.
• PLL Off: Option that sets the PLL off when self refresh occurs.
In addition, the register component found on registered DIMMs (RDIMMs) is
complemented with the following power down states:
• Self Refresh
— Clock Stopped Power Down with IBT-On
— Clock Stopped Power Down with IBT-Off
Full on – Active transfer state.
Lowest Active State Power Management (ASPM) - Longer exit latency.
Description
state is about 55% of the memory power. Exiting this mode takes
3–5 DCLK cycles.
this mode, relative to active idle state, is about 60% of the memory
power. Exiting this mode takes 3–5 DCLK cycles.
this mode, relative to active idle state, is about 87% of the memory
power. Exiting this mode takes 3–5 DCLK cycles until the first
command is allowed and 16 cycles until first data is allowed.
Terminators (IBTs) are left "on".
Terminators (IBTs) are turned "off".
Description
29