Revision History - Epson S1C31W65 Technical Manual

Revision History

Code No. Page
414063300 All New establishment
414063301 Whole Corrected the Cortex
manual System control register
Vector table offset register
System handler priority registers
Interrupt priority registers
Correcred the Cortex
Cortex
COU core → CPU
1-1 to 3 1.1 Features
Added the following annotations to Table 1.1.1.
I 2
*1 The input filter in I2C (SDA and SCL inputs) does not comply with the standard for removing noise
*2 SLEEP mode refers to deep sleep mode in the Cortex
Modified Table 1.1.1.
Instruction cache: Deleted
Package: The JEITA package name was corrected, LQFP → TQFP.
1-3 1.2 Block Diagram
Deleted Cache controller and Cache RAM from Figure 1.2.1.
2-16 2.4.2 Transition between Operating Modes
SLEEP mode
Added the following description:
The RAM retains data even in SLEEP mode.
3-2 Added a new section.
3.4 Reference Documents
4-2 4.3.1 Flash Memory Pin
Deleted the following description and note:
For the V
the "Electrical Characteristics" chapter.
Note: Always leave the V
4-3 4.6 Peripheral Circuit Control Registers
Deleted the Cache controller register from Table 4.6.1.
4-9 4.7 Instruction Cache
Deleted the section.
4-10 4.8 Control Registers
FLASHC Flash Read Cycle Register
Added a not to the RDWAIT[1:0] bit.
Notes: ...
9-4 9.4 Control Registers
WDT2 Control Register
Corrected the description of the WDTRUN[3:0] bit.
Bits 3–0 WDTRUN[3:0]
® -M0+ register names.
® -M0+ manual names.
® -M0+ Technical Reference Manual → ARM
C (I2C)
*1
spikes less than 50 ns.
SLEEP mode.
voltage, refer to "Recommended Operating Conditions, Flash programming voltage V
PP
pin open except when programming the Flash memory.
PP
• When the FLASHCWAIT.RDWAIT[1:0] bit setting is altered from 0x2 to 0x1, add two NOP
instructions immediately after that.
Program example: FLASHC->WAIT_b.RDWAIT = 1;
asm("NOP");
asm("NOP");
CLG->OSC_b.IOSCEN = 0;
These bits control WDT2 to run and stop.
0xa (WP):
Values other than 0xa (WP): Run
0xa (R):
0x0 (R):
Contents
→ Cortex ® -M0+ System Control Register
or
Cortex ® -M0+ Application Interrupt and Reset Control Register
→ Cortex ® -M0+ Vector Table Offset Register (VTOR)
→ Cortex ® -M0+ System Handler Priority Registers
→ Cortex ® -M0+ Interrupt Priority Registers
® v6-M Architecture Reference Manual、
Cortex ® -M0+Technical Reference Manual、
or
the documents introduced in Section 3.4, such as
"Cortex ® -M0+ Devices Generic User Guide"
® -M0+ processor. The RAM retains data even in
Stop
Idle
Running
REVISION HISTORY
" in
PP