Dma Transfer Requests; Control Registers; Spia Ch.n Mode Register - Epson S1C31W65 Technical Manual

14.7 DMA Transfer Requests

The SPIA has a function to generate DMA transfer requests from the causes shown in Table 14.7.1.
Cause to request
DMA transfer request flag
DMA transfer
Receive buffer Receive buffer full flag
full (SPIA_nINTF.RBFIF)
Transmit buffer Transmit buffer empty flag
empty (SPIA_nINTF.TBEIF)
The SPIA provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown
above for the number of DMA channels. A DMA transfer request is sent to the pertinent channel of the DMA con-
troller only when the DMA transfer request flag, of which DMA transfer has been enabled by the DMA transfer
request enable bit, is set. The DMA transfer request flag also serves as an interrupt flag, therefore, both the DMA
transfer request and the interrupt cannot be enabled at the same time. After a DMA transfer has completed, disable
the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the
DMA control, refer to the "DMA Controller" chapter.

14.8 Control Registers

SPIA Ch.n Mode Register

Register name Bit
SPIA_nMOD 15–12 –
11–8 CHLN[3:0]
7–6 –
5
4
3
2
1
0
Bits 15–12 Reserved
Bits 11–8 CHLN[3:0]
These bits set the bit length of transfer data.
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
Table 14.7.1 DMA Transfer Request Causes of SPIA
When data of the specified bit length is received and the
received data is transferred from the shift register to the
received data buffer
When transmit data written to the transmit data buffer is
transferred to the shift register
Bit name Initial
0x0
0x7
0x0
PUEN 0
NOCLKDIV 0
LSBFST 0
CPHA 0
CPOL 0
MST 0
Table 14.8.1 Data Bit Length Settings
SPIA_nMOD.CHLN[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
Set condition
Reset R/W
– R –
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Data bit length
16 bits
15 bits
14 bits
13 bits
12 bits
11 bits
10 bits
9 bits
8 bits
7 bits
6 bits
5 bits
4 bits
3 bits
2 bits
Setting prohibited
Clear condition
Reading the
SPIA_nRXD
register
Writing to the
SPIA_nTXD
register
Remarks
14-13