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16 16-BIT PWM TIMERS (T16B)
PRESET = 1
RUN = 1
MODEN = 1
Trigger signal
0xffff
Counter
0x0000
CMPCAPmIF = 1
Counter value → CC[15:0]
Figure 16.4.3.3 Operations in Capture Mode (Example in One-shot Up Count Mode)
Synchronous capture mode/asynchronous capture mode
The capture circuit can operate in two operating modes: synchronous capture mode and asynchronous cap-
ture mode.
Synchronous capture mode is provided to avoid the possibility of invalid data reading by capturing counter
data simultaneously with the counter being counted up/down. Set the T16B_nCCCTLm.SCS bit to 1 to set
the capture circuit to synchronous capture mode. This mode captures counter data by synchronizing the
capture signal with the counter clock.
On the other hand, asynchronous capture mode can capture counter data by detecting a trigger pulse even if
the pulse is shorter than the counter clock cycle that becomes invalid in synchronous capture mode. Set the
T16B_nCCCTLm.SCS bit to 0 to set the capture circuit to asynchronous capture mode.
(1) Synchronous capture mode
Count clock
T16B_nTC.TC[15:0]
Capture trigger signal
T16B_nCCRm.CC[15:0]
Capturing operation
(2) Asynchronous capture mode
Count clock
T16B_nTC.TC[15:0]
Capture trigger signal
T16B_nCCRm.CC[15:0]
Capturing operation
Figure 16.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode
16-16
T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3 (Trigger: falling and rising edges)
CC[15:0] → Data (R)
CC[15:0] → Data (R)
CMPCAPmIF = 1
CMPCAPmIF = 0
CMPCAPmIF = 1
Counter value → CC[15:0]
An overwrite error occurs as the T16B_nINTF.CMPCAPmIF bit has not been cleared.
0
1
2
3
1
0
1
2
3
1
Seiko Epson Corporation
CAPOWmIF = 1
Counter value → CC[15:0]
(When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3)
4
5
6
7
8
(When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3)
4
5
6
7
8
5
Software operation
Hardware operation
Captured value
(T16B_nCCRm register)
Time
9
10
11
12
13
5
9
10
11
12
13
10
11
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
14
14
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