Counter Value Read; Interrupt; Control Registers; T16 Ch.n Clock Control Register - Epson S1C31W65 Technical Manual

12 16-BIT TIMERS (T16)
0xffff
Counter
0x0000
Software control
PRESET = 1
Underflow interrupt

12.4.5 Counter Value Read

The counter value can be read out from the T16_nTC.TC[15:0] bits. However, since T16 operates on CLK_T16_n,
one of the operations shown below is required to read correctly by the CPU.
- Read the counter value twice or more and check to see if the same value is read.
- Stop the timer and then read the counter value.

12.5 Interrupt

Each T16 channel has a function to generate the interrupt shown in Table 12.5.1.
Interrupt
Underflow
T16 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only
when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information
on interrupt control, refer to the "Interrupt" chapter.

12.6 Control Registers

T16 Ch.n Clock Control Register

Register name Bit
T16_nCLK 15–9 –
8
7–4 CLKDIV[3:0]
3–2 –
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the T16 Ch.n operating clock is supplied during debugging or not.
1 (R/W): Clock supplied during debugging
0 (R/W): No clock supplied during debugging
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the T16 Ch.n operating clock (counter clock).
Bits 3–2 Reserved
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of T16 Ch.n.
12-4
Underflow cycle
PRUN = 1
PRUN = 1
Figure 12.4.4.1 Count Operations in One-shot Mode
Table 12.5.1 T16 Interrupt Function
Interrupt flag
T16_nINTF.UFIF When the counter underflows
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
Seiko Epson Corporation
PRUN = 1 PRUN = 1
PRUN = 0
Set condition
Reset R/W
– R –
H0 R/W
H0 R/W
– R
H0 R/W
S1C31W65 TECHNICAL MANUAL
T16_nTR
register setting
Time
Clear condition
Writing 1
Remarks
(Rev. 1.1)