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13 UART (UART3)
UART3 Ch.n Transmit Buffer Empty DMA Request Enable Register
Register name
Bit
UART3_nT
15–0 TBEDMAEN[15:0]
BEDMAEN
Bits 15–0 TBEDMAEN[15:0]
These bits enable the UART3 to issue a DMA transfer request to the corresponding DMA controller
channel (Ch.0–Ch.15) when a transmit buffer empty state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.
UART3 Ch.n Receive Buffer One Byte Full DMA Request Enable Register
Register name
Bit
UART3_n
15–0 RB1FDMAEN[15:0]
RB1FDMAEN
Bits 15–0 RB1FDMAEN[15:0]
These bits enable the UART3 to issue a DMA transfer request to the corresponding DMA controller
channel (Ch.0–Ch.15) when a receive buffer one byte full state has occurred.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.
UART3 Ch.n Carrier Waveform Register
Register name
Bit
UART3_nCAWF
15–8 –
7–0 CRPER[7:0]
Bits 15–8 Reserved
Bits 7–0
CRPER[7:0]
These bits set the carrier modulation output frequency. For more information, refer to "Carrier Modu-
lation."
13-16
Bit name
Initial
0x0000
Bit name
Initial
0x0000
Bit name
Initial
0x00
0x00
Seiko Epson Corporation
Reset
R/W
H0
R/W
–
Reset
R/W
H0
R/W
–
Reset
R/W
–
R
–
H0
R/W
S1C31W65 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 1.1)
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