I2C Ch.n Status And Interrupt Flag Register - Epson S1C31W65 Technical Manual

15 I 2 C (I2C)

I2C Ch.n Status and Interrupt Flag Register

Register name Bit
I2C_nINTF 15–13 –
12
11
10
9
8
7
6
5
4
3
2
1
0
Bits 15–13 Reserved
Bit 12 SDALOW
This bit indicates that SDA is set to low level.
1 (R): SDA = Low level
0 (R): SDA = High level
Bit 11 SCLLOW
This bit indicates that SCL is set to low level.
1 (R): SCL = Low level
0 (R): SCL = High level
Bit 10 BSY
This bit indicates that the I
1 (R): I
2
0 (R): I
2
Bit 9 TR
This bit indicates whether the I2C is set in transmission mode or not.
1 (R): Transmission mode
0 (R): Reception mode
Bit 8 Reserved
Bit 7 BYTEENDIF
Bit 6 GCIF
Bit 5 NACKIF
Bit 4 STOPIF
Bit 3 STARTIF
Bit 2 ERRIF
Bit 1 RBFIF
Bit 0 TBEIF
These bits indicate the I2C interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
15-22
Bit name Initial
0x0
SDALOW
SCLLOW
BSY
TR
–
BYTEENDIF
GCIF
NACKIF
STOPIF
STARTIF
ERRIF
RBFIF
TBEIF
C bus is placed into busy status.
2
C bus busy
C bus free
Seiko Epson Corporation
Reset R/W
– R –
0 H0 R
0 H0 R
0 H0/S0 R
0 H0 R
0 – R
0 H0/S0 R/W Cleared by writing 1.
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R Cleared by reading the I2C_nRXD
register.
0 H0/S0 R Cleared by writing to the I2C_nTXD
register.
Remarks
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)