Lcd8D Control Register - Epson S1C31W65 Technical Manual

LCD8DCLK.
CLKDIV[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The LCD8DCLK register settings can be altered only when the LCD8DCTL.MODEN bit = 0.

LCD8D Control Register

Register name Bit
LCD8DCTL 15–8 –
7–2 –
1
0
Bits 15–2 Reserved
Bit 1 LCDDIS
This bit enables the SEG/COM-pin discharge operations when "Display off" is selected.
1 (R/W): Enable SEG/COM-pin discharge operations
0 (R/W): Disable SEG/COM-pin discharge operations
Setting this bit to 1 configures the SEG/COM pins to output a low level when "Display off" is select-
ed. Setting to 0 configures the SEG/COM pins to enter Hi-Z status when "Display off" is selected.
Bit 0 MODEN
This bit enables the LCD8D operations.
1 (R/W): Enable LCD8D operations
0 (R/W): Disable LCD8D operations
Setting this bit to 1 starts supplying the operating clock to LCD8D.
Note: If the LCD8DCTL.MODEN bit is altered from 1 to 0 while the LCD panel is displaying, the
LCD display is automatically turned off and the LCD8DDSP.DSPC[1:0] bits are also set to
0x0. Also the LCD voltage regulator is automatically turned off and the LCD8DPWR.VCEN
bit is set to 0.
LCD8D Timing Control Register 1
Register name Bit
LCD8DTIM1 15–12 –
11–8 FRMCNT[3:0]
7–6 –
5
4–3 –
2–0 LDUTY[2:0]
Bits 15–12 Reserved
Bits 11–8 FRMCNT[3:0]
These bits set the frame frequency. For more information, refer to "Frame Frequency."
Bits 7–3 Reserved
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
Table 21.8.1 Clock Source and Division Ratio Settings
0x0
IOSC
Reserved
1/1,024
1/512
1/256
1/128
1/64
1/32
1/16
Bit name Initial
0x00
0x00
LCDDIS 0
MODEN 0
Bit name Initial
0x0
0x3
0x0
(reserved) 0
0x0
0x7
Seiko Epson Corporation
LCD8DCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/1 Reserved
1/1,024
1/512
1/256
1/128
1/64
1/32
1/16
Reset R/W
– R –
– R
H0 R/W
H0 R/W
Reset R/W
– R –
H0 R/W
– R
H0 R/W
– R
H0 R/W
21 LCD DRIVER (LCD8D)
0x3
EXOSC
1/1
Remarks
Remarks
21-21