Epson S1C31W65 Technical Manual page 338

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x4000 SPIA_0TXD
03b4 (SPIA Ch.0 Transmit
Data Register)
0x4000 SPIA_0RXD
03b6
(SPIA Ch.0 Receive
Data Register)
0x4000 SPIA_0INTF
03b8 (SPIA Ch.0 Interrupt
Flag Register)
0x4000 SPIA_0INTE
03ba
(SPIA Ch.0 Interrupt
Enable Register)
0x4000 SPIA_0TBEDMAEN
03bc (SPIA Ch.0 Transmit
Buffer Empty DMA
Request Enable
Register)
0x4000 SPIA_0RBFDMAEN
03be (SPIA Ch.0 Receive
Buffer Full DMA
Request Enable
Register)
0x4000 03c0–0x4000 03d6
Address Register name
0x4000 I2C_0CLK
03c0 (I2C Ch.0 Clock
Control Register)
0x4000 I2C_0MOD
03c2
(I2C Ch.0 Mode
Register)
0x4000 I2C_0BR
03c4
(I2C Ch.0 Baud-Rate
Register)
0x4000 I2C_0OADR
03c8 (I2C Ch.0 Own
Address Register)
0x4000 I2C_0CTL
03ca
(I2C Ch.0 Control
Register)
AP-A-14
Bit Bit name
15–0 TXD[15:0]
15–0 RXD[15:0]
15–8 –
7 BSY
6–4 –
3 OEIF
2 TENDIF
1 RBFIF
0 TBEIF
15–8 –
7–4 –
3 OEIE
2 TENDIE
1 RBFIE
0 TBEIE
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
Bit Bit name
15–9 –
8 DBRUN
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
15–8 –
7–3 –
2 OADR10
1 GCEN
0 –
15–8 –
7 –
6–0 BRT[6:0]
15–10 –
9–0 OADR[9:0]
15–8 –
7–6 –
5 MST
4 TXNACK
3 TXSTOP
2 TXSTART
1 SFTRST
0 MODEN
Seiko Epson Corporation
Initial Reset R/W
0x0000 H0 R/W
0x0000 H0 R
0x00 – R
0 H0 R
0x0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
1 H0/S0 R
0x00 – R
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
Initial Reset R/W
0x00 – R
0 H0 R/W
0x0 – R
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0 – R
0x00 – R
0 – R
0x7f H0 R/W
0x00 – R
0x000 H0 R/W
0x00 – R
0x0 – R
0 H0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R/W
0 H0 R/W
0 H0 R/W
S1C31W65 TECHNICAL MANUAL
Remarks
–
–
–
Cleared by writing 1.
Cleared by reading the
SPIA_0RXD register.
Cleared by writing to the
SPIA_0TXD register.
–
–
–
I C (I2C) Ch.0
2
Remarks
–
–
–
–
–
(Rev. 1.1)