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11 SUPPLY VOLTAGE DETECTOR (SVD4)
11.2 Input Pins and External Connection
11.2.1 Input Pins
Table 11.2.1.1 shows the SVD4 input pins.
Pin name
EXSVDnx
If the port is shared with the EXSVDnx pin and other functions, the EXSVDnx function must be assigned to the
port before SVD4 Ch.n can be activated. For more information, refer to the "I/O Ports" chapter.
11.2.2 External Connection
Figure 11.2.2.1 Connection between EXSVDn Pin and External Power Supply
For the EXSVDnx pin input voltage range and the EXSVD input impedance, refer to "Supply Voltage Detector
Characteristics" in the "Electrical Characteristics" chapter.
11.3 Clock Settings
11.3.1 SVD4 Operating Clock
When using SVD4 Ch.n, the SVD4 operating clock CLK_SVD4_n must be supplied to SVD4 Ch.n from the clock
generator.
The CLK_SVD4_n supply should be controlled as in the procedure shown below.
1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
2. Enable the clock source in the clock generator if it is stopped (refer to "Clock Generator" in the "Power Supply,
Reset, and Clocks" chapter).
3. Set the following SVD4_nCLK register bits:
- SVD4_nCLK.CLKSRC[1:0] bits
- SVD4_nCLK.CLKDIV[2:0] bits
4. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)
The CLK_SVD4_n frequency should be set to around 32 kHz.
11.3.2 Clock Supply in SLEEP Mode
When using SVD4 Ch.n during SLEEP mode, the SVD4 operating clock CLK_SVD4_n must be configured so that
it will keep supplying by writing 0 to the CLGOSC.xxxxSLPC bit for the CLK_SVD4_n clock source.
If the CLGOSC.xxxxSLPC bit for the CLK_SVD4_n clock source is 1, the CLK_SVD4_n clock source is deac-
tivated during SLEEP mode and SVD4 Ch.n stops with the register settings maintained at those before entering
SLEEP mode. After the CPU returns to normal mode, CLK_SVD4_n is supplied and the SVD4 Ch.n operation re-
sumes.
11-2
Table 11.2.1.1 SVD4 Input Pins
I/O
Initial status
A
*
A (Hi-Z)
*
External power
EXSVDnx
supply/regulator
etc.
Seiko Epson Corporation
External power supply voltage detection pin
* Indicates the status when the pin is configured for SVD4.
SVD4 Ch.n
SVD
analog block
R
EXSVD
V
SS
(Clock source selection)
(Clock division ratio selection = Clock frequency setting)
Function
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
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