Remc3 Data Bit Counter Control Register - Epson S1C31W65 Technical Manual

18 IR REMOTE CONTROLLER (REMC3)
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of the REMC3.
REMC3CLK.
CLKDIV[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The REMC3CLK register settings can be altered only when the REMC3DBCTL.MODEN bit = 0.

REMC3 Data Bit Counter Control Register

Register name Bit
REMC3DBCTL 15–10 –
9
8
7–5 –
4
3
2
1
0
Bits 15–10 Reserved
Bit 9 PRESET
This bit resets the internal counters (16-bit counter for data signal generation and 8-bit counter for car-
rier generation).
1 (W): Reset
0 (W): Ineffective
1 (R): Resetting in progress
0 (R): Resetting finished or normal operation
Before the counter can be reset using this bit, the REMC3DBCTL.MODEN bit must be set to 1.
This bit is cleared to 0 after the counter reset operation has finished or when 1 is written to the
REMC3DBCTL.REMCRST bit.
Bit 8 PRUN
This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and
8-bit counter for carrier generation).
1 (W): Start counting
0 (W): Stop counting
1 (R): Counting
0 (R): Idle
18-8
Table 18.7.1 Clock Source and Division Ratio Settings
0x0
IOSC
1/32,768
1/16,384
1/8,192
1/4,096
1/2,048
1/1,024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Bit name Initial
0x00
PRESET 0
PRUN 0
0x0
REMOINV 0
BUFEN 0
TRMD 0
REMCRST 0
MODEN 0
Seiko Epson Corporation
REMC3CLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/1 1/32,768
1/16,384
1/8,192
1/4,096
1/2,048
1/1,024
1/512
1/256 1/256
1/128 1/128
1/64 1/64
1/32 1/32
1/16 1/16
1/8 1/8
1/4 1/4
1/2 1/2
1/1 1/1
Reset R/W
– R –
H0/S0 R/W Cleared by writing 1 to the
REMC3DBCTL.REMCRST bit.
H0/S0 R/W
– R –
H0 R/W
H0 R/W
H0 R/W
H0 W
H0 R/W
0x3
EXOSC
1/1
Remarks
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)