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21 LCD DRIVER (LCD8D)
Table 21.3.4.1 Frame Frequency Settings (when f
LCD8DTIM1.
FRMCNT[3:0] bits
1/8 duty
0xf
16.0
0xe
17.1
0xd
18.3
0xc
19.7
0xb
21.3
0xa
23.3
0x9
25.6
0x8
28.4
0x7
32.0
0x6
36.6
0x5
42.7
0x4
51.2
0x3
64.0
0x2
85.3
0x1
128.0
0x0
256.0
21.4 LCD Power Supply
The LCD drive voltages V
lator and LCD voltage booster). One or all voltages can also be applied from outside the IC.
The drive bias can be selected from 1/3 bias and 1/2 bias using the LCD8DPWR.BIASSEL bit.
21.4.1 Internal Generation Mode
This mode generates all the LCD drive voltages V
mode, set the LCD8DPWR.EXVCSEL bit to 0 and set both the LCD8DPWR.VCEN and LCD8DPWR.BSTEN
bits to 1 to turn both the LCD voltage regulator and LCD voltage booster on. The LCD8DPWR.RESISEL[1:0] bits
should be set to 0x0 to disable the internal LCD voltage dividing resistors. Figure 21.4.1.1 shows an external con-
nection example for internal generation mode.
C
P2
C
P1
V
C3
V
C2
V
C1
When 1/3 bias is selected
(LCD8DPWR.BIASSEL bit = 1)
Figure 21.4.1.1 External Connection Example for Internal Generation Mode
21.4.2 External Voltage Application Mode 1
In this mode, all the LCD drive voltages V
voltage application mode 1, set the LCD8DPWR.EXVCSEL bit to 1 and set both the LCD8DPWR.VCEN
and LCD8DPWR.BSTEN bits to 0 to turn both the LCD voltage regulator and LCD voltage booster off. The
LCD8DPWR.RESISEL[1:0] bits should be set to 0x0 to disable the internal LCD voltage dividing resistors. Figure
21.4.2.1 shows an external connection example for external voltage application mode 1.
21-4
1/7 duty
1/6 duty
18.3
21.3
19.5
22.8
20.9
24.4
22.5
26.3
24.4
28.4
26.6
31.0
29.3
34.1
32.5
37.9
36.6
42.7
41.8
48.8
48.8
56.9
58.5
68.3
73.1
85.3
97.5
113.8
146.3
170.7
292.6
341.3
to V
can be generated by the internal LCD power supply circuit (LCD voltage regu-
C1
C3
C1
C
LCD4
C
C
C
LCD1
LCD2
LCD3
to V
C1
C3
Seiko Epson Corporation
CLK_LCD8D
Frame frequency [Hz]
1/5 duty
1/4 duty
25.6
32.0
27.3
34.1
29.3
36.6
31.5
39.4
34.1
42.7
37.2
46.5
41.0
51.2
45.5
56.9
51.2
64.0
58.5
73.1
68.3
85.3
81.9
102.4
102.4
128.0
136.5
170.7
204.8
256.0
409.6
512.0
to V
on the chip. To put LCD8D into internal generation
C3
C
C
V
V
V
When 1/2 bias is selected
(LCD8DPWR.BIASSEL bit = 0)
are applied from outside the IC. To put LCD8D into external
= 32,768 Hz)
1/3 duty
1/2 duty
42.7
64.0
45.5
68.3
48.8
73.1
52.5
78.8
56.9
85.3
62.1
93.1
68.3
102.4
75.9
113.8
85.3
128.0
97.5
146.3
113.8
170.7
136.5
204.8
170.7
256.0
227.6
341.3
341.3
512.0
1,024.0
682.7
1,024.0
2,048.0
P2
C
LCD4
P1
C3
C2
C1
C
C
LCD1
LCD3
S1C31W65 TECHNICAL MANUAL
Static
128.0
136.5
146.3
157.5
170.7
186.2
204.8
227.6
256.0
292.6
341.3
409.6
512.0
682.7
(Rev. 1.1)
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