Epson S1C31W65 Technical Manual page 358

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x4000 DMACCFG
1004 (DMAC Configuration
Register)
0x4000 DMACCPTR
1008 (DMAC Control Data
Base Pointer Register)
0x4000 DMACACPTR
100c (DMAC Alternate
Control Data Base
Pointer Register)
0x4000 DMACSWREQ
1014
(DMAC Software
Request Register)
0x4000 DMACRMSET
1020 (DMAC Request
Mask Set Register)
0x4000 DMACRMCLR
1024 (DMAC Request
Mask Clear Register)
0x4000 DMACENSET
1028 (DMAC Enable Set
Register)
0x4000 DMACENCLR
102c (DMAC Enable Clear
Register)
0x4000 DMACPASET
1030 (DMAC Primary-Alter-
nate Set Register)
0x4000 DMACPACLR
1034 (DMAC Primary-Alter-
nate Clear Register)
0x4000 DMACPRSET
1038 (DMAC Priority Set
Register)
0x4000 DMACPRCLR
103c
(DMAC Priority Clear
Register)
AP-A-34
Bit Bit name
31–24 –
23–16 –
15–8 –
7–1 –
0 MSTEN
31–7 CPTR[31:7]
6–0 CPTR[6:0]
31–0 ACPTR[31:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 SWREQ[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 RMSET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 RMCLR[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENSET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 ENCLR[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PASET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PACLR[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PRSET[3:0]
31–24 –
23–16 –
15–8 –
7–4 –
3–0 PRCLR[3:0]
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0x00 – R
0x00 – R
0x00 – R
– – W
0x000 H0 R/W
0000
0x00 H0 R
– H0 R
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
0x00 – R
0x00 – R
0x00 – R
0x0 – R
0x0 H0 R/W
– – R
– – R
– – R
– – R
– – W
S1C31W65 TECHNICAL MANUAL
Remarks
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(Rev. 1.1)