Operations - Epson S1C31W65 Technical Manual

2.3.4 Operations

Oscillation start time and oscillation stabilization waiting time
The oscillation start time refers to the time after the oscillator circuit is enabled until the oscillation signal is ac-
tually sent to the internal circuits. The oscillation stabilization waiting time refers to the time it takes the clock
to stabilize after the oscillation starts. To avoid malfunctions of the internal circuits due to an unstable clock
during this period, the oscillator circuit includes an oscillation stabilization waiting circuit that can disable sup-
plying the clock to the system until the designated time has elapsed. Figure 2.3.4.1 shows the relationship be-
tween the oscillation start time and the oscillation stabilization waiting time.
Digitized oscillation waveform
Oscillator circuit output clock
Oscillation stabilization waiting completion flag
Figure 2.3.4.1 Oscillation Start Time and Oscillation Stabilization Waiting Time
The oscillation stabilization waiting times for the IOSC, OSC1, and OSC3 oscillator circuits can be set using
the CLGIOSC.IOSCWT[1:0] bits, CLGOSC1.OSC1WT[1:0] bits, and CLGOSC3.OSC3WT[2:0] bits, respec-
tively. To check whether the oscillation stabilization waiting time is set properly and the clock is stabilized im-
mediately after the oscillation starts or not, monitor the oscillation clock using the FOUT output function.
The oscillation stabilization waiting time for the IOSC oscillator circuit is fixed at 16 IOSCCLK clocks when
the IOSC frequency is 2 MHz or lower. When the frequency is 8 MHz or higher, set to 8 IOSCCLK clocks or
more.
The oscillation stabilization waiting time for the OSC1 oscillator circuit should be set to 16,384 OSC1CLK
clocks or more when crystal oscillator is selected, or 4,096 OSC1CLK clocks or more when internal oscillator
is selected.
The oscillation stabilization waiting time for the OSC3 oscillator circuit should be set to 1,024 OSC3CLK
clocks or more when crystal/ceramic oscillator is selected, or 16 OSC3CLK clocks or more when internal oscil-
lator is selected.
When the oscillation stabilization waiting operation has completed, the oscillator circuit sets the oscillation sta-
bilization waiting completion flag and starts clock supply to the internal circuits.
Note: The oscillation stabilization waiting time is always expended at start of oscillation even if the os-
cillation stabilization waiting completion flag has not be cleared to 0.
When the oscillation startup control circuit in the OSC1 oscillator circuit is enabled by setting the CLGOSC1.OS-
C1BUP bit to 1, it uses the high-gain oscillation inverter for a set period of time (startup boosting operation) after
the oscillator circuit is enabled (by setting the CLGOSC.OSC1EN bit to 1) to reduce oscillation start time. Note,
however, that the oscillation operation may become unstable if there is a large gain differential between normal
operation and startup boosting operation. Furthermore, the oscillation start time being actually reduced depends
on the characteristics of the resonator used. Figure 2.3.4.2 shows an operation example when the oscillation start-
up control circuit is used.
(1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled)
Oscillator circuit enable
(CLGOSC.OSC1EN)
Oscillation inverter
Oscillation waveform
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
Oscillator circuit enable
(∗OSC∗EN)
Oscillation waveform
(∗OSC∗CLK)
(∗OSC∗STAIF)
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
System supply waiting time
Oscillation start time
Oscillation stabilization waiting time
INV1N[1:0] setting gain
Normal operation
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