Clg Interrupt Flag Register - Epson S1C17W22 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS
Bits 15–12 Reserved
Bits 11–10 OSC3FQ[1:0]
These bits set the oscillation frequency when the internal oscillator is selected as the OSC3 oscillator.
Bits 9–8 OSC3MD[1:0]
These bits select an oscillator type of the OSC3 oscillator circuit.
Bits 7–6 Reserved
Bits 5–4 OSC3INV[1:0]
These bits set the oscillation inverter gain when crystal/ceramic oscillator is selected as the OSC3 os-
cillator type.
Bit 3 Reserved
Bits 2–0 OSC3WT[2:0]
These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit.
Table 2.6.12 OSC3 Oscillation Stabilization Waiting Time Setting

CLG Interrupt Flag Register

Register name Bit
CLGINTF 15–8 –
7
6
5
4
3
2
1
0
2-22
Table 2.6.9 OSC3 Internal Oscillator Frequency Setting
CLGOSC3.OSC3FQ[1:0] bits
0x3
0x2
0x1
0x0
Table 2.6.10 OSC3 Oscillator Type Selection
CLGOSC3.OSC3MD[1:0] bits
0x3
0x2
0x1
0x0
Table 2.6.11 OSC3 Oscillation Inverter Gain Setting
CLGOSC3.OSC3INV[1:0] bits
0x3
0x2
0x1
0x0
CLGOSC3.OSC3WT[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name Initial
0x00
– 0x0
(reserved)
OSC1STPIF
IOSCTEDIF
–
OSC3STAIF
OSC1STAIF
IOSCSTAIF
Seiko Epson Corporation
OSC3 internal oscillator frequency
4 MHz
2 MHz
1 MHz
500 kHz
OSC3 oscillator type
Reserved
Crystal/ceramic oscillator
CR oscillator
Internal oscillator
Inverter gain
Max.
↑
↓
Min.
Oscillation stabilization waiting time
65,536 clocks
16,384 clocks
4,096 clocks
1,024 clocks
256 clocks
64 clocks
16 clocks
4 clocks
Reset R/W
– R –
– R
0 H0 R
0 H0 R/W Cleared by writing 1.
0 H0 R/W
0 – R –
0 H0 R/W Cleared by writing 1.
0 H0 R/W
0 H0 R/W
Remarks
S1C17W22/W23 TECHNICAL MANUAL
(Rev. 1.3)