Spia Ch.n Control Register - Epson S1C31W65 Technical Manual

Cmos 32-bit single chip microcontroller
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14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
Bits 7–6
Reserved
Bit 5
PUEN
This bit enables pull-up/down of the input pins.
1 (R/W): Enable pull-up/down
0 (R/W): Disable pull-up/down
For more information, refer to "Input Pin Pull-Up/Pull-Down Function."
Bit 4
NOCLKDIV
This bit selects SPICLKn in master mode. This setting is ineffective in slave mode.
1 (R/W): SPICLKn frequency = CLK_SPIAn frequency ( = 16-bit timer operating clock frequency)
0 (R/W): SPICLKn frequency = 16-bit timer output frequency / 2
For more information, refer to "SPIA Operating Clock."
Bit 3
LSBFST
This bit configures the data format (input/output permutation).
1 (R/W): LSB first
0 (R/W): MSB first
Bit 2
CPHA
Bit 1
CPOL
These bits set the SPI clock phase and polarity. For more information, refer to "SPI Clock (SPICLKn)
Phase and Polarity."
Bit 0
MST
This bit sets the SPIA operating mode (master mode or slave mode).
1 (R/W): Master mode
0 (R/W): Slave mode
Note: The SPIA_nMOD register settings can be altered only when the SPIA_nCTL.MODEN bit = 0.

SPIA Ch.n Control Register

Register name
Bit
SPIA_nCTL
15–8 –
7–2 –
1
0
Bits 15–2 Reserved
Bit 1
SFTRST
This bit issues software reset to SPIA.
1 (W):
Issue software reset
0 (W):
Ineffective
1 (R):
Software reset is executing.
0 (R):
Software reset has finished. (During normal operation)
Setting this bit resets the SPIA shift register and transfer bit counter. This bit is automatically cleared
after the reset processing has finished.
Bit 0
MODEN
This bit enables the SPIA operations.
1 (R/W): Enable SPIA operations (In master mode, the operating clock is supplied.)
0 (R/W): Disable SPIA operations (In master mode, the operating clock is stopped.)
Note: If the SPIA_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being
sent/received cannot be guaranteed. When setting the SPIA_nCTL.MODEN bit to 1 again after
that, be sure to write 1 to the SPIA_nCTL.SFTRST bit as well.
14-14
Bit name
Initial
0x00
0x00
SFTRST
0
MODEN
0
Seiko Epson Corporation
Reset
R/W
R
R
H0
R/W
H0
R/W
S1C31W65 TECHNICAL MANUAL
Remarks
(Rev. 1.1)

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