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REVISION HISTORY
Code No.
Page
414063301
10-4
10.4.2 Real-Time Clock Counter Operations
Corrective operation when a value out of the effective range is set
Added a note.
Note: Do not set the RTCMON.RTCMOL[3:0] bits to 0x0 if the RTCMON.RTCMOH bit = 0.
10-11
10.6 Control Registers
RTCA Month/Day Register
Bit 12
Bits 11–8 RTCMOL[3:0]
Added a note.
Notes: ...
15-1
15.1 Overview
Added the following description:
• The input filter for the SDA and SCL inputs does not comply with the standard for removing noise
15-7, 9
15.4.3 Data Reception in Master Mode
Data receiving procedure
Added Step 1. (The old step numbers were carried down in order.)
1. When receiving one-byte data, write 1 to the I2C_nCTL.TXNACK bit.
Modified Figure 15.4.3.2.
A flow for Step 1 was added.
15-9
15.4.3 Data Reception in Master Mode
Data reception using DMA
Corrected the description.
This automates the data receiving procedure Steps 6, 8, and 10 described above.
15-13 to 14 15.4.6 Data Reception in Slave Mode
Data receiving procedure
Added Step 1. (The old step numbers were carried down in order.)
1. When receiving one-byte data, write 1 to the I2C_nCTL.TXNACK bit.
Modified Figure 15.4.6.2.
A flow for Step 1 was added.
16-5
16.4.2 Counter Block Operations
MAX counter data register
Added a note.
Note: When rewriting the MAX value, the new MAX value should be written after the counter has been
23-1
23.2 Recommended Operating Conditions
Added "(V
*1 The potential variation of the V
*6 The component values should be determined after evaluating operations using an actual mounting
23-7
23.6 Flash Memory Characteristics
Added an annotation.
*1 The potential variation of the V
25-1
25 Package
The JEITA package name was corrected, LQFP → TQFP.
AP-A-3
Appendix A List of Peripheral Circuit Control Registers
Deleted the CACHE Control Register.
AP-D-1
Appendix D Measures Against Noise
Added a description.
Noise Measures for Input Pins Connected to Signal with High Driving Capability Such As Power Supply
RTCMOH
• Be sure to avoid setting the RTCAMON.RTCMOH/RTCMOL[3:0] bits to 0x00.
spikes less than 50 ns.
reset to the previously set MAX value.
= 0 V) *1" and the following annotations:
SS
ground potential of the MCU mounting board while the Flash is being programmed, as it affects the
Flash memory characteristics (programming count).
board.
ground potential of the MCU mounting board while the Flash is being programmed, as it affects the
Flash memory characteristics (programming count).
Contents
voltage should be suppressed to within ±0.3 V on the basis of the
SS
voltage should be suppressed to within ±0.3 V on the basis of the
SS
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