Epson S1C31W65 Technical Manual page 35

Oscillation start procedure for the OSC3 oscillator circuit
Follow the procedure shown below to start oscillation of the OSC3 oscillator circuit.
1. Write 1 to the CLGINTF.OSC3STAIF bit.
2. Write 1 to the CLGINTE.OSC3STAIE bit.
3. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection)
4. Configure the following CLGOSC1 register bits:
- CLGOSC3.OSC3MD bit
- CLGOSC3.OSC3WT[2:0] bits
In addition to the above, configure the following bits when using the crystal/ceramic oscillator:
- CLGOSC3.OSC3INV[1:0] bits
Configure the following bits when using the internal oscillator:
- CLGOSC3.OSC3FQ[2:0] bits
5. When using the internal oscillator, set the CLGTRIM2.OSC3SAJ[6:0] bits as necessary.
6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection)
7. When using the crystal/ceramic oscillator, assign the OSC3 oscillator input/output functions to the ports.
(Refer to the "I/O Ports" chapter.)
8. Write 1 to the CLGOSC.OSC3EN bit.
9. OSC3CLK can be used if the CLGINTF.OSC3STAIF bit = 1 after an interrupt occurs.
The setting values of the CLGOSC3.OSC3INV[1:0], CLGOSC3.OSC3WT[2:0], and CLGTRIM2.
OSC3SAJ[6:0] bits should be determined after performing evaluation using the populated circuit board.
Note: Make sure the CLGOSC.OSC3EN bit is set to 0 (while the OSC3 oscillation is halted) when set-
ting the CLGTRIM2.OSC3SAJ[6:0] bits.
System clock switching
The CPU boots using IOSCCLK as SYSCLK. After booting, the clock source of SYSCLK can be switched ac-
cording to the processing speed required. The SYSCLK frequency can also be set by selecting the clock source
division ratio, this makes it possible to run the CPU at the most suitable performance for the process to be ex-
ecuted. The CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are used for this control.
The CLGSCLK register bits are protected against writings by the system protect function, therefore, the system protec-
tion must be removed by writing 0x0096 to the SYSPROT.PROT[15:0] bits before the register setting can be altered.
For the transition between the operating modes including the system clock switching, refer to "Operating Mode."
Clock control in SLEEP mode
Whether the clock sources being operated are stopped or not when the CPU enters SLEEP mode (deep sleep
mode) can be selected in each source individually. This allows the CPU to fast switch between SLEEP mode
and RUN mode, and the peripheral circuits to continue operating without disabling the clock in SLEEP mode.
The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and CLGOSC.EXOSCSLPC bits
are used for this control. Figure 2.3.4.3 shows a control example.
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
(Clear interrupt flag)
(Enable interrupt)
(Select oscillator type)
(Set oscillation stabilization waiting time)
(Set oscillation inverter gain)
(Select frequency)
(Finely adjust oscillation frequency)
(Start oscillation)
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
2-13