Interrupts; Dma Transfer Requests - Epson S1C31W65 Technical Manual

13 UART (UART3)

13.7 Interrupts

The UART3 has a function to generate the interrupts shown in Table 13.7.1.
Interrupt
End of transmission UART3_nINTF.TENDIF When the UART3_nINTF.TBEIF bit = 1
Framing error UART3_nINTF.FEIF
Parity error UART3_nINTF.PEIF
Overrun error UART3_nINTF.OEIF
Receive buffer two UART3_nINTF.RB2FIF When the second received data byte is
bytes full
Receive buffer UART3_nINTF.RB1FIF When the first received data byte is load-
one byte full
Transmit buffer empty UART3_nINTF.TBEIF
The UART3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the
CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more
information on interrupt control, refer to the "Interrupt" chapter.

13.8 DMA Transfer Requests

The UART3 has a function to generate DMA transfer requests from the causes shown in Table 13.8.1.
Cause to request DMA
transfer
Receive buffer Receive buffer one byte full flag
one byte full (UART3_nINTF.RB1FIF)
Transmit buffer empty Transmit buffer empty flag
(UART3_nINTF.TBEIF)
The UART3 provides DMA transfer request enable bits corresponding to each DMA transfer request flag shown
above for the number of DMA channels. A DMA transfer request is sent to the pertinent channel of the DMA con-
troller only when the DMA transfer request flag, of which DMA transfer has been enabled by the DMA transfer
request enable bit, is set. The DMA transfer request flag also serves as an interrupt flag, therefore, both the DMA
transfer request and the interrupt cannot be enabled at the same time. After a DMA transfer has completed, disable
the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the
DMA control, refer to the "DMA Controller" chapter.
13-10
Table 13.7.1 UART3 Interrupt Function
Interrupt flag
after the stop bit has been sent
Refer to the "Receive Errors."
Refer to the "Receive Errors."
Refer to the "Receive Errors."
loaded to the receive data buffer in which
the first byte is already received
ed to the emptied receive data buffer
When transmit data written to the trans-
mit data buffer is transferred to the shift
register
Table 13.8.1 DMA Transfer Request Causes of UART3
DMA transfer request flag
Seiko Epson Corporation
Set condition
Set condition
When the first received data
byte is loaded to the emptied
receive data buffer
When transmit data written
to the transmit data buffer is
transferred to the shift register
Clear condition
Writing 1 or software reset
Writing 1, reading received
data that encountered an
error, or software reset
Writing 1, reading received
data that encountered an
error, or software reset
Writing 1 or software reset
Reading received data or
software reset
Reading data to empty
the receive data buffer or
software reset
Writing transmit data
Clear condition
Reading data to empty
the receive data buffer or
software reset
Writing transmit data
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)