Epson S1C31W65 Technical Manual page 350

Cmos 32-bit single chip microcontroller
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APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address
Register name
0x4000
I2C_1TBEDMAEN
06d4
(I2C Ch.1 Transmit
Buffer Empty DMA
Request Enable
Register)
0x4000
I2C_1RBFDMAEN
06d6
(I2C Ch.1 Receive
Buffer Full DMA
Request Enable
Register)
0x4000 0700–0x4000 070c
Address
Register name
0x4000
SNDACLK
0700
(SNDA Clock Control
Register)
0x4000
SNDASEL
0702
(SNDA Select
Register)
0x4000
SNDACTL
0704
(SNDA Control
Register)
0x4000
SNDADAT
0706
(SNDA Data
Register)
0x4000
SNDAINTF
0708
(SNDA Interrupt Flag
Register)
0x4000
SNDAINTE
070a
(SNDA Interrupt
Enable Register)
0x4000
SNDAEMDMAEN
070c
(SNDA Sound Buffer
Empty DMA Request
Enable Register)
0x4000 0720–0x4000 0732
Address
Register name
0x4000
REMC3CLK
0720
(REMC3 Clock Con-
trol Register)
AP-A-26
Bit
Bit name
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
Bit
Bit name
15–9 –
8
DBRUN
7
6–4 CLKDIV[2:0]
3–2 –
1–0 CLKSRC[1:0]
15–12 –
11–8 STIM[3:0]
7–3 –
2
SINV
1–0 MOSEL[1:0]
15–9 –
8
SSTP
7–1 –
0
MODEN
15
MDTI
14
MDRS
13–8 SLEN[5:0]
7–0 SFRQ[7:0]
15–9 –
8
SBSY
7–2 –
1
EMIF
0
EDIF
15–8 –
7–2 –
1
EMIE
0
EDIE
15–8 –
7–4 –
3–0 EMDMAEN[3:0]
Bit
Bit name
15–9 –
8
DBRUN
7–4 CLKDIV[3:0]
3–2 –
1–0 CLKSRC[1:0]
Seiko Epson Corporation
Initial
Reset
R/W
0x00
R
0x0
R
0x0
H0
R/W
0x00
R
0x0
R
0x0
H0
R/W
Sound Generator (SNDA)
Initial
Reset
R/W
0x00
R
0
H0
R/W
0
R
0x0
H0
R/W
0x0
R
0x0
H0
R/W
0x0
R
0x0
H0
R/W
0x00
R
0
H0
R/W
0x0
H0
R/W
0x00
R
0
H0
R/W
0x00
R
0
H0
R/W
0
H0
R/W
0
H0
R/W
0x00
H0
R/W
0xff
H0
R/W
0x00
R
0
H0
R
0x00
R
1
H0
R
0
H0
R/W
0x00
R
0x00
R
0
H0
R/W
0
H0
R/W
0x00
R
0x0
R
0x0
H0
R/W
IR Remote Controller (REMC3)
Initial
Reset
R/W
0x00
R
0
H0
R/W
0x0
H0
R/W
0x0
R
0x0
H0
R/W
S1C31W65 TECHNICAL MANUAL
Remarks
Remarks
Cleared by writing to the
SNDADAT register.
Cleared by writing 1 or writ-
ing to the SNDADAT register.
Remarks
(Rev. 1.1)

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