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ACK1
RESET
VECTOR
FETCH
DECODER
V
DD
I
NTERNAL
PULLUP
DEVICE
IRQ1/V
PP
Addr.
Register Name
IRQ Status/Control Register
$001E
14.4.1 IRQ1/V
Pin
PP
MC68HC(7)08KH12
Rev. 1.1
—
Freescale Semiconductor
V
DD
CLR
D
Q
CK
IRQ1
FF
MODE1
Figure 14-1. IRQ Module Block Diagram
Table 14-1. IRQ I/O Port Register Summary
Bit 7
Read:
0
Write:
(ISCR)
Reset:
0
A logic zero on the IRQ1/V
IRQ1 latch. A vector fetch, software clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ1/V
and low-level-sensitive. With MODE1 set, both of the following actions
must occur to clear IRQ1:
SYNCHRO-
NIZER
IMASK1
HIGH
VOLTAGE
DETECT
6
5
4
0
0
0
0
0
0
= Unimplemented
pin can latch an interrupt request into the
PP
pin is both falling-edge-sensitive
PP
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF1
3
2
1
IRQF1
0
IMASK1 MODE1
ACK1
0
0
0
Advance Information
IRQ1
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
Bit 0
0
215
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