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7.8 SIM Registers
7.8.1 Break Status Register (BSR)
MC68HC(7)08KH12
Rev. 1.1
—
Freescale Semiconductor
The SIM has three memory mapped registers.
mapping of these registers.
Address
$FE00
$FE01
$FE03
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
Address:
$FE00
Bit 7
6
Read:
R
R
Write:
Reset:
R
= Reserved
Figure 7-20. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait
or stop mode after exiting from a break interrupt. Clear SBSW
by writing a logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break
interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing zero to the SBSW bit clears
it.
Table 7-4. SIM Registers
Register
BSR
RSR
BFCR
5
4
R
R
Table 7-4
shows the
Access Mode
User
User
User
3
2
1
SBSW
R
R
Note 1
0
1. Writing a logic zero clears SBSW
Advance Information
Bit 0
R
83
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