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13.3 Functional Description
CGMXCLK
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COPEN (FROM SIM)
COP DISABLE
(COPD FROM CONFIG)
RESET
COPCTL WRITE
COP RATE SEL
(COPRS FROM CONFIG)
Addr.
Register Name
Configuration Register
$001F
(CONFIG)
COP Control Register
$FFFF
(COPCTL)
† One-time writable register
Advance Information
208
Figure 13-1
shows the structure of the COP module.
12-BIT SIM COUNTER
COP CLOCK
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
Figure 13-1. COP Block Diagram
Table 13-1. COP I/O Port Register Summary
Bit 7
Read:
0
Write:
†
Reset:
0
Read:
Write:
Reset:
= Unimplemented
RESET STATUS REGISTER
6
5
4
0
0
0
SSREC
0
0
0
Low byte of reset vector
Clear COP counter
Unaffected by reset
RESET CIRCUIT
3
2
1
Bit 0
COPRS
STOP
COPD
0
0
0
MC68HC(7)08KH12
Rev. 1.1
—
Freescale Semiconductor
0
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