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Addr.
Name
$0050
USB HUB Downstream Port 1
$0051
Control Register (HDP1CR)
USB HUB Downstream Port 2
$0052
Control Register (HDP2CR)
USB HUB Downstream Port 3
$0053
Control Register (HDP3CR)
USB HUB Downstream Port 4
$0054
Control Register (HDP4CR)
$0055
USB SIE Timing Interrupt Register
$0056
USB SIE Timing Status Register
$0057
USB HUB Address Register
$0058
USB HUB Interrupt Register 0
$0059
$005A
USB HUB Control Register 0
$005B
USB HUB Endpoint1 Control &
$005C
Data Register (HCDR)
$005D
USB HUB Status Register (HSR)
USB HUB Root Port Control
$005E
Register (HRPCR)
$005F
Figure 2-2. Control, Status, and Data Registers (Continued)
MC68HC(7)08KH12
Rev. 1.1
—
Freescale Semiconductor
Bit 7
R:
Unimplemented
W:
R:
PEN1
W:
R:
PEN2
W:
R:
PEN3
W:
R:
PEN4
W:
R:
Unimplemented
W:
R:
SOFF
(SIETIR)
W:
R:
RSTF
(SIETSR)
W:
R:
USBEN
(HADDR)
W:
R:
TXDF
(HIR0)
W:
R:
Unimplemented
W:
R:
TSEQ
(HCR0)
W:
R:
STALL1
W:
R:
RSEQ
W:
R:
0
W:
R:
Unimplemented
W:
6
5
4
LOWSP1
RST1
RESUM1 SUSP1
LOWSP2
RST2
RESUM2 SUSP2
LOWSP3
RST3
RESUM3 SUSP3
LOWSP4
RST4
RESUM4 SUSP4
EOF2F
EOPF
TRANF
0
LOCKF
0
RSTFR
LOCKFR SOFFR EOF2FR EOPFR TRANFR
ADD6
ADD5
ADD4
RXDF
0
0
STALL0
TXE
RXE
PNEW
PCHG5
PCHG4
SETUP
TX1ST
0
TX1STR
0
0
RESUM0 SUSPND
= Unimplemented
3
2
1
0
D1+
0
D2+
0
D3+
0
D4+
SOFIE
EOF2IE
EOPIE
0
0
0
ADD3
ADD2
ADD1
0
TXDIE
RXDIE
TXDFR
TPSIZ3
TPSIZ2
TPSIZ1
PCHG3
PCHG2
PCHG1
RPSIZ3
RPSIZ2
RPSIZ1
0
D0+
R
= Reserved
Advance Information
Bit 0
D1–
D2–
D3–
D4–
TRANIE
0
ADD0
0
RXDFR
TPSIZ0
PCHG0
RPSIZ0
D0–
41
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