Port D Data Register (Ptd); Data Direction Register D (Ddrd) - Freescale Semiconductor MC68HC08KH12 Datasheet

12.6.1 Port D Data Register (PTD)

12.6.2 Data Direction Register D (DDRD)

MC68HC(7)08KH12 Rev. 1.1
—
Freescale Semiconductor
The port D data register contains a data latch for each of the eight port D
pins.
Address: $0003
Bit 7 6
Read:
PTD7 PTD6
Write:
Reset:
Alternate
KBD7 KBD6
Function:
Figure 12-10. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
The port D pullups are automatically enabled if the respective pin is
configured as a keyboard interrupt. (See
Interrupt Functional
The port-D keyboard interrupt enable bits, KBDIE7—KBDIE0, in the
port-D keyboard interrupt enable register (KBDIER), enable the port D
pins as external interrupt pins.
Module (KBI).
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
5 4
PTD5 PTD4 PTD3
Unaffected by reset
KBD5 KBD4 KBD3
15.4.1 Port-D Keyboard
Description.)
See Section 15. Keyboard Interrupt
3 2 1
PTD2 PTD1
KBD2 KBD1
Advance Information
Bit 0
PTD0
KBD0
193