Freescale Semiconductor MC68HC08KH12 Datasheet page 112

NOTE:
Advance Information
112
an initial frequency error, (f
percent.
The inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See
Manual and Automatic PLL Bandwidth
clock cycles, n , is required to ascertain that the PLL is within the
ACQ
tracking mode entry tolerance, ∆
certain number of clock cycles, n
is within the lock mode entry tolerance, ∆
time, t , is an integer multiple of n
ACQ
time, t , is an integer multiple of n
AL
In manual mode, it is usually necessary to wait considerably longer than
t before selecting the PLL clock (See
LOCKMAX
Selector Circuit.), because the factors described in
Influences on Reaction Time
Automatic bandwidth mode is recommended for most users.
, of not more than ±100
– f )/f
DES ORIG DES
V
   
8
DDA
= ------------ - ------------ -
t
   
ACQ
f K
RDV ACQ
V
   
4
DDA
= ------------ - ----------- -
t
   
AL
f K
RDV TRK
= + +
t t t 256t
LOCKMAX ACQ AL
Modes.) A certain number of
, before exiting acquisition mode. A
TRK
, is required to ascertain that the PLL
TRK
LOCK
/f , and the acquisition to lock
ACQ RDV
/f .
TRK RDV
may slow the lock time considerably.
VRDV
8.4.5
. Therefore, the acquisition
8.4.8 Base Clock
8.9.2 Parametric
MC68HC(7)08KH12 Rev. 1.1
—
Freescale Semiconductor