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8.6.2 PLL Bandwidth Control Register (PBWC)
Advance Information
104
Table 8-3. PRE[1:0] Programming
PRE1
PRE0
0
0
1
1
The PLL bandwidth control register:
•
Indicates when the PLL is locked
•
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
Address:
$003B
Bit 7
6
Read:
LOCK
AUTO
Write:
Reset:
0
0
= Unimplemented
Figure 8-4. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
Since this CGM is optimized a frequency output of 48MHz for the USB
module, automatic control should be set. Reset clears the AUTO bit.
1 = Automatic bandwidth control (recommended)
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
P
Prescaler Multiplier
0
0
1
1
0
2
1
3
5
4
3
0
0
ACQ
0
0
0
1
2
4
8
2
1
Bit 0
0
0
0
0
0
0
MC68HC(7)08KH12
Rev. 1.1
—
Freescale Semiconductor
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