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15.6.3 Port-F Keyboard Interrupt Registers
15.6.3.1 Port-F Keyboard Status and Control Register
MC68HC(7)08KH12
Rev. 1.1
—
Freescale Semiconductor
4. Write to the ACKF bit in the keyboard status and control register
to clear any false interrupts.
5. Clear the IMASKF bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
•
Flags keyboard interrupt requests.
•
Acknowledges keyboard interrupt requests.
•
Masks keyboard interrupt requests.
•
Controls keyboard interrupt triggering sensitivity.
Address: $0040
Bit 7
Read:
0
Write:
Reset:
0
= Unimplemented
Figure 15-8. Port-F Keyboard Status and Control Register (KBFSCR)
Bits [7:4] — Not used
These read-only bits always read as logic 0s.
KEYFF — Port-F Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on
port-F. Reset clears the KEYFF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
6
5
4
0
0
0
0
0
0
3
2
1
KEYFF
0
IMASKF
ACKF
0
0
0
Advance Information
Bit 0
MODEF
0
237
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