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NOTE:
NOTE:
Advance Information
50
The CONFIG register is a special register containing one-time writable
latches after each reset. Upon a reset, the CONFIG register defaults to
the predetermined settings as shown in
Address:
$001F
Bit 7
6
Read:
0
0
Write:
Reset:
0
0
= Unimplemented
Figure 5-1. Configuration Register (CONFIG)
SSREC — Short stop recovery bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
COPRS — COP reset period selection bit
1 = COP reset cycle is (2
0 = COP reset cycle is (2
STOP — STOP instruction enable bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP disable bit
COPD disables the COP module.
Operating Properly
1 = COP module disabled
0 = COP module enabled
Figure
5
4
3
0
0
SSREC
0
0
0
13
4
–2
)×CGMXCLK
18
4
–2
)×CGMXCLK
See Section 13. Computer
(COP).
MC68HC(7)08KH12
5-1.
2
1
Bit 0
COPRS
STOP
COPD
0
0
0
Rev. 1.1
—
Freescale Semiconductor
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